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Zachary Snow
2a2d819baa
- assertions, gen case, and inout - simplify block codegen - remove blank lines in tasks with no inputs
17 lines
313 B
Systemverilog
17 lines
313 B
Systemverilog
module Module(x, y);
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inout x, y;
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parameter DIR = 1;
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if (DIR)
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assign x = y;
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else
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assign y = x;
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endmodule
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module top;
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wire inp = 1;
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wire out1, out2;
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Module #(0) fwd(inp, out1);
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Module #(1) rev(out2, inp);
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initial $display("%b %b %b", inp, out1, out2);
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endmodule
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