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Zachary Snow
2a2d819baa
- assertions, gen case, and inout - simplify block codegen - remove blank lines in tasks with no inputs
17 lines
299 B
Systemverilog
17 lines
299 B
Systemverilog
module Module;
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parameter X = 1;
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case (X)
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1: initial $display("A");
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2: initial $display("B");
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default: initial $display("C");
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3: ;
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endcase
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endmodule
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module top;
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Module #(1) a();
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Module #(2) b();
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Module #(3) c();
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Module #(4) d();
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endmodule
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