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Zachary Snow
8c967ea9c7
- cast functions in separate scopes are no longer omitted or removed - package item reordering excludes locally declared names - test runner ensures output is stable after first iteration
16 lines
376 B
Systemverilog
16 lines
376 B
Systemverilog
module top;
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parameter YES = 1;
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if (YES) begin
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function automatic [31:0] help;
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input [31:0] inp;
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help = inp + 1;
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endfunction
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initial $display("A %0d", help(0));
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end
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function automatic [31:0] help;
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input [31:0] inp;
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help = inp + 2;
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endfunction
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initial $display("B %0d", help(0));
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endmodule
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