allow type declarations in tasks and functions (#321)

Co-authored-by: Zachary Snow <zach@zachjs.com>

src/Language/SystemVerilog/Parser/Parse.y

@@ -1226,6 +1226,7 @@ DeclsAndStmts :: { ([Decl], [Stmt]) }
 DeclOrStmt :: { ([Decl], [Stmt]) }
   : DeclTokens(";")    { parseDTsAsDeclOrStmt $1 }
   | ParameterDecl(";") { ($1, []) }
+  | Typedef            { ([$1], []) }
 
 ParameterDecl(delim) :: { [Decl] }
   : ParameterDeclKW           DeclAsgns delim { makeParamDecls $1 (Implicit Unspecified []) $2 }

test/core/tf_typedef.sv

@@ -0,0 +1,17 @@
+module top;
+    task t;
+        typedef byte u;
+        $display("t %b", u'('1));
+    endtask
+    function integer f;
+        input reg signed i;
+        typedef shortint v;
+        $display("i %b", v'(i));
+        return $bits(v);
+    endfunction
+    initial begin
+        t();
+        $display("f %b", f(0));
+        $display("f %b", f(1));
+    end
+endmodule

test/core/tf_typedef.v

@@ -0,0 +1,19 @@
+module top;
+    task t;
+        $display("t %b", 8'hFF);
+    endtask
+    function integer f;
+        input reg signed i;
+        reg [15:0] j;
+        begin
+            j = i;
+            $display("i %b", j);
+            f = 16;
+        end
+    endfunction
+    initial begin
+        t;
+        $display("f %b", f(0));
+        $display("f %b", f(1));
+    end
+endmodule