From f41cc5bcea6cfa09b3898e6b7b84f92c30676dc6 Mon Sep 17 00:00:00 2001 From: Akihiko Odaki Date: Sat, 22 Nov 2025 13:17:56 +0900 Subject: [PATCH] allow type declarations in tasks and functions (#321) Co-authored-by: Zachary Snow --- src/Language/SystemVerilog/Parser/Parse.y | 1 + test/core/tf_typedef.sv | 17 +++++++++++++++++ test/core/tf_typedef.v | 19 +++++++++++++++++++ 3 files changed, 37 insertions(+) create mode 100644 test/core/tf_typedef.sv create mode 100644 test/core/tf_typedef.v diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y index 2fb2475..bfb1551 100644 --- a/src/Language/SystemVerilog/Parser/Parse.y +++ b/src/Language/SystemVerilog/Parser/Parse.y @@ -1226,6 +1226,7 @@ DeclsAndStmts :: { ([Decl], [Stmt]) } DeclOrStmt :: { ([Decl], [Stmt]) } : DeclTokens(";") { parseDTsAsDeclOrStmt $1 } | ParameterDecl(";") { ($1, []) } + | Typedef { ([$1], []) } ParameterDecl(delim) :: { [Decl] } : ParameterDeclKW DeclAsgns delim { makeParamDecls $1 (Implicit Unspecified []) $2 } diff --git a/test/core/tf_typedef.sv b/test/core/tf_typedef.sv new file mode 100644 index 0000000..8619b47 --- /dev/null +++ b/test/core/tf_typedef.sv @@ -0,0 +1,17 @@ +module top; + task t; + typedef byte u; + $display("t %b", u'('1)); + endtask + function integer f; + input reg signed i; + typedef shortint v; + $display("i %b", v'(i)); + return $bits(v); + endfunction + initial begin + t(); + $display("f %b", f(0)); + $display("f %b", f(1)); + end +endmodule diff --git a/test/core/tf_typedef.v b/test/core/tf_typedef.v new file mode 100644 index 0000000..3526567 --- /dev/null +++ b/test/core/tf_typedef.v @@ -0,0 +1,19 @@ +module top; + task t; + $display("t %b", 8'hFF); + endtask + function integer f; + input reg signed i; + reg [15:0] j; + begin + j = i; + $display("i %b", j); + f = 16; + end + endfunction + initial begin + t; + $display("f %b", f(0)); + $display("f %b", f(1)); + end +endmodule