use strict State and Writer monads

src/Convert/DuplicateGenvar.hs

@@ -6,7 +6,7 @@
 
 module Convert.DuplicateGenvar (convert) where
 
-import Control.Monad.State
+import Control.Monad.State.Strict
 import qualified Data.Set as Set
 
 import Convert.Traverse

src/Convert/EmptyArgs.hs

@@ -8,7 +8,7 @@
 
 module Convert.EmptyArgs (convert) where
 
-import Control.Monad.Writer
+import Control.Monad.Writer.Strict
 import qualified Data.Set as Set
 
 import Convert.Traverse

src/Convert/Enum.hs

@@ -19,7 +19,7 @@
 
 module Convert.Enum (convert) where
 
-import Control.Monad.Writer
+import Control.Monad.Writer.Strict
 import Data.List (elemIndices)
 import qualified Data.Set as Set
 

src/Convert/FuncRoutine.hs

@@ -10,7 +10,7 @@
 
 module Convert.FuncRoutine (convert) where
 
-import Control.Monad.Writer
+import Control.Monad.Writer.Strict
 import qualified Data.Set as Set
 
 import Convert.Traverse

src/Convert/Interface.hs

@@ -8,7 +8,7 @@ module Convert.Interface (convert) where
 
 import Data.List (isPrefixOf)
 import Data.Maybe (mapMaybe)
-import Control.Monad.Writer
+import Control.Monad.Writer.Strict
 import qualified Data.Map.Strict as Map
 
 import Convert.Scoper

src/Convert/Jump.hs

@@ -10,8 +10,8 @@
 
 module Convert.Jump (convert) where
 
-import Control.Monad.State
-import Control.Monad.Writer
+import Control.Monad.State.Strict
+import Control.Monad.Writer.Strict
 
 import Convert.Traverse
 import Language.SystemVerilog.AST

src/Convert/KWArgs.hs

@@ -10,7 +10,7 @@
 module Convert.KWArgs (convert) where
 
 import Data.List (elemIndex, sortOn)
-import Control.Monad.Writer
+import Control.Monad.Writer.Strict
 import qualified Data.Map.Strict as Map
 
 import Convert.Traverse

src/Convert/Logic.hs

@@ -25,8 +25,8 @@
 
 module Convert.Logic (convert) where
 
-import Control.Monad.State
-import Control.Monad.Writer
+import Control.Monad.State.Strict
+import Control.Monad.Writer.Strict
 import qualified Data.Map.Strict as Map
 import qualified Data.Set as Set
 

src/Convert/NamedBlock.hs

@@ -10,7 +10,7 @@
 
 module Convert.NamedBlock (convert) where
 
-import Control.Monad.State
+import Control.Monad.State.Strict
 import qualified Data.Set as Set
 
 import Convert.Traverse

src/Convert/NestPI.hs

@@ -6,7 +6,7 @@
 
 module Convert.NestPI (convert, reorder) where
 
-import Control.Monad.Writer
+import Control.Monad.Writer.Strict
 import Data.Maybe (mapMaybe)
 import qualified Data.Map.Strict as Map
 import qualified Data.Set as Set

src/Convert/Package.hs

@@ -25,8 +25,8 @@
 
 module Convert.Package (convert) where
 
-import Control.Monad.State
-import Control.Monad.Writer
+import Control.Monad.State.Strict
+import Control.Monad.Writer.Strict
 import qualified Data.Map.Strict as Map
 import qualified Data.Set as Set
 

src/Convert/ParamType.hs

@@ -7,7 +7,7 @@
 
 module Convert.ParamType (convert) where
 
-import Control.Monad.Writer
+import Control.Monad.Writer.Strict
 import Data.Either (isLeft)
 import Data.Maybe (isJust, isNothing, fromJust)
 import qualified Data.Map.Strict as Map

src/Convert/Scoper.hs

@@ -42,7 +42,7 @@ module Convert.Scoper
     , scopeModuleItemT
     ) where
 
-import Control.Monad.State
+import Control.Monad.State.Strict
 import Data.Functor.Identity (runIdentity)
 import Data.Maybe (isNothing)
 import qualified Data.Map.Strict as Map

src/Convert/SizeCast.hs

@@ -7,7 +7,7 @@
 
 module Convert.SizeCast (convert) where
 
-import Control.Monad.Writer
+import Control.Monad.Writer.Strict
 import Data.List (isPrefixOf)
 
 import Convert.ExprUtils

src/Convert/StarPort.hs

@@ -6,7 +6,7 @@
 
 module Convert.StarPort (convert) where
 
-import Control.Monad.Writer
+import Control.Monad.Writer.Strict
 import qualified Data.Map.Strict as Map
 
 import Convert.Traverse

src/Convert/Traverse.hs

@@ -98,8 +98,8 @@ module Convert.Traverse
 ) where
 
 import Data.Functor.Identity (Identity, runIdentity)
-import Control.Monad.State
-import Control.Monad.Writer
+import Control.Monad.State.Strict
+import Control.Monad.Writer.Strict
 import Language.SystemVerilog.AST
 
 type MapperM m t = t -> m t

src/Convert/UnbasedUnsized.hs

@@ -17,7 +17,7 @@
 
 module Convert.UnbasedUnsized (convert) where
 
-import Control.Monad.Writer
+import Control.Monad.Writer.Strict
 import Data.Maybe (catMaybes)
 import qualified Data.Map.Strict as Map
 

src/Convert/UnpackedArray.hs

@@ -14,7 +14,7 @@
 
 module Convert.UnpackedArray (convert) where
 
-import Control.Monad.State
+import Control.Monad.State.Strict
 import qualified Data.Set as Set
 
 import Convert.Scoper

src/Language/SystemVerilog/Parser.hs

@@ -6,7 +6,7 @@ module Language.SystemVerilog.Parser
     ) where
 
 import Control.Monad.Except
-import Control.Monad.State
+import Control.Monad.State.Strict
 import qualified Data.Map.Strict as Map
 import Language.SystemVerilog.AST (AST)
 import Language.SystemVerilog.Parser.Lex (lexStr)

src/Language/SystemVerilog/Parser/Parse.y

@@ -16,7 +16,7 @@
 module Language.SystemVerilog.Parser.Parse (parse) where
 
 import Control.Monad.Except
-import Control.Monad.State
+import Control.Monad.State.Strict
 import Data.Maybe (fromMaybe)
 import Language.SystemVerilog.AST
 import Language.SystemVerilog.Parser.ParseDecl

src/Language/SystemVerilog/Parser/Preprocess.hs

@@ -14,7 +14,7 @@ module Language.SystemVerilog.Parser.Preprocess
     ) where
 
 import Control.Monad.Except
-import Control.Monad.State
+import Control.Monad.State.Strict
 import Data.Char (ord)
 import Data.List (dropWhileEnd, tails, isPrefixOf, findIndex)
 import Data.Maybe (isJust, fromJust)