default implicit output ports to logic

src/Language/SystemVerilog/Parser/ParseDecl.hs

@@ -389,7 +389,9 @@ parseDTsAsDecls mode l0 =
         (tps, l7) = takeTrips    l6 initReason
         pos = tokPos $ head l0
         base = von dir t
-        t = tf rs
+        t = case (dir, tf rs) of
+                (Output, Implicit sg _) -> IntegerVector TLogic sg rs
+                (_, typ) -> typ
         decls =
             CommentDecl ("Trace: " ++ show pos) :
             map (\(x, a, e) -> base x a e) tps

test/core/output_implicit.sv

@@ -0,0 +1,4 @@
+module mod(output x, y);
+    initial x = 1;
+    assign y = 1;
+endmodule

test/core/output_implicit.v

@@ -0,0 +1,4 @@
+module mod(output reg x, output wire y);
+    initial x = 1;
+    assign y = 1;
+endmodule

test/core/output_implicit_tb.v

@@ -0,0 +1,4 @@
+module top;
+    wire o1, o2;
+    mod m(o1, o2);
+endmodule