From e0d425d976dcc010aecf6fd36251bc004ace670c Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Tue, 27 Jul 2021 17:20:09 -0400
Subject: [PATCH] default implicit output ports to logic

---
 src/Language/SystemVerilog/Parser/ParseDecl.hs | 4 +++-
 test/core/output_implicit.sv                   | 4 ++++
 test/core/output_implicit.v                    | 4 ++++
 test/core/output_implicit_tb.v                 | 4 ++++
 4 files changed, 15 insertions(+), 1 deletion(-)
 create mode 100644 test/core/output_implicit.sv
 create mode 100644 test/core/output_implicit.v
 create mode 100644 test/core/output_implicit_tb.v

diff --git a/src/Language/SystemVerilog/Parser/ParseDecl.hs b/src/Language/SystemVerilog/Parser/ParseDecl.hs
index 04e489c..28de04c 100644
--- a/src/Language/SystemVerilog/Parser/ParseDecl.hs
+++ b/src/Language/SystemVerilog/Parser/ParseDecl.hs
@@ -389,7 +389,9 @@ parseDTsAsDecls mode l0 =
         (tps, l7) = takeTrips    l6 initReason
         pos = tokPos $ head l0
         base = von dir t
-        t = tf rs
+        t = case (dir, tf rs) of
+                (Output, Implicit sg _) -> IntegerVector TLogic sg rs
+                (_, typ) -> typ
         decls =
             CommentDecl ("Trace: " ++ show pos) :
             map (\(x, a, e) -> base x a e) tps
diff --git a/test/core/output_implicit.sv b/test/core/output_implicit.sv
new file mode 100644
index 0000000..a5b267d
--- /dev/null
+++ b/test/core/output_implicit.sv
@@ -0,0 +1,4 @@
+module mod(output x, y);
+    initial x = 1;
+    assign y = 1;
+endmodule
diff --git a/test/core/output_implicit.v b/test/core/output_implicit.v
new file mode 100644
index 0000000..94255f9
--- /dev/null
+++ b/test/core/output_implicit.v
@@ -0,0 +1,4 @@
+module mod(output reg x, output wire y);
+    initial x = 1;
+    assign y = 1;
+endmodule
diff --git a/test/core/output_implicit_tb.v b/test/core/output_implicit_tb.v
new file mode 100644
index 0000000..7a14b7a
--- /dev/null
+++ b/test/core/output_implicit_tb.v
@@ -0,0 +1,4 @@
+module top;
+    wire o1, o2;
+    mod m(o1, o2);
+endmodule