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fix premature logic to wire conversion

This commit is contained in:
Zachary Snow 2019-09-17 23:59:19 -04:00
parent 82218848fc
commit df3620d3a0
1 changed files with 15 additions and 8 deletions
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23
src/Convert/Logic.hs
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@ -60,7 +60,7 @@ convert =
convertDescription :: Ports -> Description -> Description convertDescription :: Ports -> Description -> Description
convertDescription ports orig = convertDescription ports orig =
if shouldConvert if shouldConvert
then traverseModuleItems conversion orig then converted
else orig else orig
where where
shouldConvert = case orig of shouldConvert = case orig of
@ -69,18 +69,23 @@ convertDescription ports orig =
PackageItem _ -> True PackageItem _ -> True
Package _ _ _ -> False Package _ _ _ -> False
Directive _ -> False Directive _ -> False
origIdents = execWriter (collectModuleItemsM regIdents orig)
fixed = traverseModuleItems fixModuleItem orig
fixedIdents = execWriter (collectModuleItemsM regIdents fixed)
conversion = traverseDecls convertDecl . convertModuleItem conversion = traverseDecls convertDecl . convertModuleItem
idents = execWriter (collectModuleItemsM regIdents orig) converted = traverseModuleItems conversion fixed
convertModuleItem :: ModuleItem -> ModuleItem
fixModuleItem :: ModuleItem -> ModuleItem
-- rewrite bad continuous assignments to use procedural assignments -- rewrite bad continuous assignments to use procedural assignments
convertModuleItem (Assign Nothing lhs expr) = fixModuleItem (Assign Nothing lhs expr) =
if Set.disjoint usedIdents idents if Set.disjoint usedIdents origIdents
then Assign Nothing lhs expr then Assign Nothing lhs expr
else AlwaysC AlwaysComb $ AsgnBlk AsgnOpEq lhs expr else AlwaysC AlwaysComb $ AsgnBlk AsgnOpEq lhs expr
where where
usedIdents = execWriter $ collectNestedLHSsM lhsIdents lhs usedIdents = execWriter $ collectNestedLHSsM lhsIdents lhs
-- rewrite port bindings to use temporary nets where necessary -- rewrite port bindings to use temporary nets where necessary
convertModuleItem (Instance moduleName params instanceName rs bindings) = fixModuleItem (Instance moduleName params instanceName rs bindings) =
if null newItems if null newItems
then Instance moduleName params instanceName rs bindings then Instance moduleName params instanceName rs bindings
else Generate $ map GenModuleItem $ else Generate $ map GenModuleItem $
@ -92,7 +97,7 @@ convertDescription ports orig =
newItems = concat newItemsList newItems = concat newItemsList
fixBinding :: PortBinding -> (PortBinding, [ModuleItem]) fixBinding :: PortBinding -> (PortBinding, [ModuleItem])
fixBinding (portName, Just expr) = fixBinding (portName, Just expr) =
if portDir /= Just Output || Set.disjoint usedIdents idents if portDir /= Just Output || Set.disjoint usedIdents origIdents
then ((portName, Just expr), []) then ((portName, Just expr), [])
else ((portName, Just tmpExpr), items) else ((portName, Just tmpExpr), items)
where where
@ -112,11 +117,13 @@ convertDescription ports orig =
++ show expr ++ " connected to output port " ++ show expr ++ " connected to output port "
++ portName ++ " of " ++ instanceName ++ portName ++ " of " ++ instanceName
fixBinding other = (other, []) fixBinding other = (other, [])
fixModuleItem other = other
-- rewrite variable declarations to have the correct type -- rewrite variable declarations to have the correct type
convertModuleItem (MIPackageItem (Decl (Variable dir (IntegerVector _ sg mr) ident a me))) = convertModuleItem (MIPackageItem (Decl (Variable dir (IntegerVector _ sg mr) ident a me))) =
MIPackageItem $ Decl $ Variable dir (t mr) ident a me MIPackageItem $ Decl $ Variable dir (t mr) ident a me
where where
t = if sg /= Unspecified || Set.member ident idents t = if Set.member ident fixedIdents
then IntegerVector TReg sg then IntegerVector TReg sg
else Net TWire sg else Net TWire sg
convertModuleItem other = other convertModuleItem other = other