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zero-pad sized integrals no larger than 256 bits

This commit is contained in:
Zachary Snow 2020-08-09 17:36:25 -04:00
parent 50a6966a4f
commit ddaa7ff6c6
1 changed files with 1 additions and 1 deletions
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2
src/Language/SystemVerilog/AST/Number.hs
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@ -237,7 +237,7 @@ showBasedDigits base size values kinds =
padList '0' sizeDigits digits
else if leadingXZ && size < 0 then
removeExtraPadding digits
else if leadingXZ || (32 > size && size > 0) then
else if leadingXZ || (256 >= size && size > 0) then
padList '0' sizeDigits digits
else
digits