From ddaa7ff6c60ae2567d52d54001a6fbd58c136881 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Sun, 9 Aug 2020 17:36:25 -0400
Subject: [PATCH] zero-pad sized integrals no larger than 256 bits

---
 src/Language/SystemVerilog/AST/Number.hs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/Language/SystemVerilog/AST/Number.hs b/src/Language/SystemVerilog/AST/Number.hs
index 0122b24..e1941e8 100644
--- a/src/Language/SystemVerilog/AST/Number.hs
+++ b/src/Language/SystemVerilog/AST/Number.hs
@@ -237,7 +237,7 @@ showBasedDigits base size values kinds =
         padList '0' sizeDigits digits
     else if leadingXZ && size < 0 then
         removeExtraPadding digits
-    else if leadingXZ || (32 > size && size > 0) then
+    else if leadingXZ || (256 >= size && size > 0) then
         padList '0' sizeDigits digits
     else
         digits