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fix PackedArray handling of bit select followed by range select

This commit is contained in:
Zachary Snow 2019-04-11 18:29:30 -04:00
parent 88c537c93f
commit da9452bd26
2 changed files with 34 additions and 16 deletions
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35
src/Convert/PackedArray.hs
View File

@ -195,16 +195,31 @@ rewriteModuleItem info =
hi = BinOp Sub (BinOp Add lo (BinOp Mul (rangeSize range) size)) (Number "1") hi = BinOp Sub (BinOp Add lo (BinOp Mul (rangeSize range) size)) (Number "1")
IndexedPlus -> (BinOp Add (BinOp Mul size (fst range)) base, BinOp Mul size (snd range)) IndexedPlus -> (BinOp Add (BinOp Mul size (fst range)) base, BinOp Mul size (snd range))
IndexedMinus -> (BinOp Add (BinOp Mul size (fst range)) base, BinOp Mul size (snd range)) IndexedMinus -> (BinOp Add (BinOp Mul size (fst range)) base, BinOp Mul size (snd range))
---- TODO: I'm not sure how these should be handled yet. rewriteExpr (orig @ (Range (Bit (Ident x) idxInner) modeOuter rangeOuter)) =
----rewriteExpr (orig @ (Range (Bit (Ident x) idxInner) modeOuter rangeOuter)) = if Map.member x typeDims
---- if Map.member x typeDims then Range (Ident x') mode' range'
---- then Range (Ident x') mode' range' else orig
---- else orig where
---- where (dimInner, dimOuter) = dims x
---- (dimInner, dimOuter) = dims x x' = ':' : x
---- x' = ':' : x mode' = IndexedPlus
---- mode' = idxInner' = orientIdx dimInner idxInner
---- range' = rangeOuterReverseIndexed =
(BinOp Add (fst rangeOuter) (BinOp Sub (snd rangeOuter)
(Number "1")), snd rangeOuter)
(baseOuter, lenOuter) =
case modeOuter of
IndexedPlus ->
endianCondRange dimOuter rangeOuter rangeOuterReverseIndexed
IndexedMinus ->
endianCondRange dimOuter rangeOuterReverseIndexed rangeOuter
NonIndexed ->
(endianCondExpr dimOuter (snd rangeOuter) (fst rangeOuter), rangeSize rangeOuter)
idxOuter' = orientIdx dimOuter baseOuter
start = BinOp Mul idxInner' (rangeSize dimOuter)
base = simplify $ BinOp Add start idxOuter'
len = lenOuter
range' = (base, len)
rewriteExpr other = other rewriteExpr other = other
rewriteLHS :: LHS -> LHS rewriteLHS :: LHS -> LHS

15
test/basic/flatten.sv
View File

@ -6,12 +6,15 @@ module name(clock, in, out); \
initial out[1+a] = 0; \ initial out[1+a] = 0; \
initial out[2+a] = 0; \ initial out[2+a] = 0; \
always @(posedge clock) begin \ always @(posedge clock) begin \
/*$display($time, `" name ", out[0+a][1+b+:1]);*/ \ $display($time, `" name @+ ", out[0+a][1+b+:1]); \
/*$display($time, `" name ", out[0+a][1+b+:1]);*/ \ $display($time, `" name @+ ", out[1+a][1+b+:1]); \
/*$display($time, `" name ", out[1+a][1+b+:1]);*/ \ $display($time, `" name @+ ", out[2+a][1+b+:1]); \
/*$display($time, `" name ", out[1+a][1+b+:1]);*/ \ $display($time, `" name @+ ", out[0+a][1+b+:2]); \
/*$display($time, `" name ", out[2+a][1+b+:1]);*/ \ $display($time, `" name @+ ", out[1+a][1+b+:2]); \
/*$display($time, `" name ", out[2+a][1+b+:1]);*/ \ $display($time, `" name @+ ", out[2+a][1+b+:2]); \
$display($time, `" name @: ", out[0+a][1+b:1+b]); \
$display($time, `" name @: ", out[1+a][1+b:1+b]); \
$display($time, `" name @: ", out[2+a][1+b:1+b]); \
\ \
out[2+a][4+b] = out[2+a][3+b]; \ out[2+a][4+b] = out[2+a][3+b]; \
out[2+a][3+b] = out[2+a][2+b]; \ out[2+a][3+b] = out[2+a][2+b]; \