mirror of https://github.com/zachjs/sv2v.git
fixed handling of 3+ dimensional packed arrays
This commit is contained in:
Zachary Snow
parent
afad70de1a
commit
88c537c93f
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@ -116,7 +116,7 @@ flattenRanges rs =
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rY = endianCondRange r2 rYY rYN
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rN = endianCondRange r2 rNY rNN
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r = endianCondRange r1 rY rN
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rs' = (tail $ tail rs) ++ [r]
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rs' = r : (tail $ tail rs)
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flattenRangesHelp :: Range -> Range -> Range
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flattenRangesHelp (s1, e1) (s2, e2) =
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@ -185,6 +185,7 @@ rewriteModuleItem info =
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x' = ':' : x
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mode' = mode
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size = rangeSize dimOuter
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base = endianCondExpr dimOuter (snd dimOuter) (fst dimOuter)
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range' =
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case mode of
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NonIndexed ->
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@ -192,8 +193,8 @@ rewriteModuleItem info =
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where
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lo = BinOp Mul size (snd range)
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hi = BinOp Sub (BinOp Add lo (BinOp Mul (rangeSize range) size)) (Number "1")
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IndexedPlus -> (BinOp Mul size (fst range), BinOp Mul size (snd range))
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IndexedMinus -> (BinOp Mul size (fst range), BinOp Mul size (snd range))
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IndexedPlus -> (BinOp Add (BinOp Mul size (fst range)) base, BinOp Mul size (snd range))
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IndexedMinus -> (BinOp Add (BinOp Mul size (fst range)) base, BinOp Mul size (snd range))
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---- TODO: I'm not sure how these should be handled yet.
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----rewriteExpr (orig @ (Range (Bit (Ident x) idxInner) modeOuter rangeOuter)) =
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---- if Map.member x typeDims
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@ -0,0 +1,84 @@
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`define CASE(name, dims, a, b, c) \
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module name(clock, in, out); \
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input wire clock, in; \
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output logic dims out; \
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initial out[0+a] = 0; \
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initial out[1+a] = 0; \
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initial out[2+a] = 0; \
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always @(posedge clock) begin \
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\
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out[2+a][4+b][1+c] = out[2+a][4+b][0+c]; \
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out[2+a][4+b][0+c] = out[2+a][3+b][1+c]; \
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out[2+a][3+b][1+c] = out[2+a][3+b][0+c]; \
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out[2+a][3+b][0+c] = out[2+a][2+b][1+c]; \
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out[2+a][2+b][1+c] = out[2+a][2+b][0+c]; \
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out[2+a][2+b][0+c] = out[2+a][1+b][1+c]; \
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out[2+a][1+b][1+c] = out[2+a][1+b][0+c]; \
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out[2+a][1+b][0+c] = out[2+a][0+b][1+c]; \
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out[2+a][0+b][1+c] = out[2+a][0+b][0+c]; \
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out[2+a][0+b][0+c] = out[1+a][4+b][1+c]; \
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\
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out[1+a][4+b][1+c] = out[1+a][4+b][0+c]; \
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out[1+a][4+b][0+c] = out[1+a][3+b][1+c]; \
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out[1+a][3+b][1+c] = out[1+a][3+b][0+c]; \
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out[1+a][3+b][0+c] = out[1+a][2+b][1+c]; \
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out[1+a][2+b][1+c] = out[1+a][2+b][0+c]; \
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out[1+a][2+b][0+c] = out[1+a][1+b][1+c]; \
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out[1+a][1+b][1+c] = out[1+a][1+b][0+c]; \
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out[1+a][1+b][0+c] = out[1+a][0+b][1+c]; \
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out[1+a][0+b][1+c] = out[1+a][0+b][0+c]; \
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out[1+a][0+b][0+c] = out[0+a][4+b][1+c]; \
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\
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out[0+a][4+b][1+c] = out[0+a][4+b][0+c]; \
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out[0+a][4+b][0+c] = out[0+a][3+b][1+c]; \
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out[0+a][3+b][1+c] = out[0+a][3+b][0+c]; \
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out[0+a][3+b][0+c] = out[0+a][2+b][1+c]; \
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out[0+a][2+b][1+c] = out[0+a][2+b][0+c]; \
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out[0+a][2+b][0+c] = out[0+a][1+b][1+c]; \
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out[0+a][1+b][1+c] = out[0+a][1+b][0+c]; \
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out[0+a][1+b][0+c] = out[0+a][0+b][1+c]; \
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out[0+a][0+b][1+c] = out[0+a][0+b][0+c]; \
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out[0+a][0+b][0+c] = in; \
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\
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end \
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endmodule
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`CASE(A1, [2:0][4:0][1:0], 0, 0, 0)
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`CASE(A2, [0:2][0:4][1:0], 0, 0, 0)
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`CASE(A3, [0:2][4:0][1:0], 0, 0, 0)
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`CASE(A4, [2:0][0:4][1:0], 0, 0, 0)
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`CASE(B1, [3:1][5:1][1:0], 1, 1, 0)
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`CASE(B2, [1:3][1:5][1:0], 1, 1, 0)
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`CASE(B3, [1:3][5:1][1:0], 1, 1, 0)
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`CASE(B4, [3:1][1:5][1:0], 1, 1, 0)
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`CASE(C1, [4:2][6:2][1:0], 2, 2, 0)
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`CASE(C2, [2:4][2:6][1:0], 2, 2, 0)
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`CASE(C3, [2:4][6:2][1:0], 2, 2, 0)
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`CASE(C4, [4:2][2:6][1:0], 2, 2, 0)
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`CASE(D1, [5:3][6:2][1:0], 3, 2, 0)
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`CASE(D2, [3:5][2:6][1:0], 3, 2, 0)
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`CASE(D3, [3:5][6:2][1:0], 3, 2, 0)
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`CASE(D4, [5:3][2:6][1:0], 3, 2, 0)
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`CASE(E1, [2:0][4:0][0:1], 0, 0, 0)
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`CASE(E2, [0:2][0:4][0:1], 0, 0, 0)
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`CASE(E3, [0:2][4:0][0:1], 0, 0, 0)
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`CASE(E4, [2:0][0:4][0:1], 0, 0, 0)
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`CASE(F1, [5:3][6:2][1:0], 3, 2, 0)
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`CASE(F2, [3:5][2:6][1:0], 3, 2, 0)
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`CASE(F3, [3:5][6:2][1:0], 3, 2, 0)
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`CASE(F4, [5:3][2:6][1:0], 3, 2, 0)
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`CASE(G1, [5:3][6:2][2:1], 3, 2, 1)
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`CASE(G2, [3:5][2:6][2:1], 3, 2, 1)
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`CASE(G3, [3:5][6:2][2:1], 3, 2, 1)
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`CASE(G4, [5:3][2:6][2:1], 3, 2, 1)
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`CASE(H1, [5:3][6:2][1:2], 3, 2, 1)
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`CASE(H2, [3:5][2:6][1:2], 3, 2, 1)
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`CASE(H3, [3:5][6:2][1:2], 3, 2, 1)
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`CASE(H4, [5:3][2:6][1:2], 3, 2, 1)
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@ -0,0 +1,2 @@
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// iverilog supports multi-dimensional packed arrays
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`include "flatten_three.sv"
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@ -0,0 +1,43 @@
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`define FOO(tag) \
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wire [29:0] tag``one_out, tag``two_out, tag``thr_out, tag``fou_out; \
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tag``1 tag``one(.clock(clock), .in(in), .out(tag``one_out)); \
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tag``2 tag``two(.clock(clock), .in(in), .out(tag``two_out)); \
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tag``3 tag``thr(.clock(clock), .in(in), .out(tag``thr_out)); \
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tag``4 tag``fou(.clock(clock), .in(in), .out(tag``fou_out)); \
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integer tag``i; \
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initial begin \
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for (tag``i = 0; tag``i < 40; tag``i++) begin \
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#2; \
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$display(`"tag", $time, ": %h %30b %30b %30b %30b", in, \
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tag``one_out, tag``two_out, tag``thr_out, tag``fou_out); \
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end \
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end
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module top;
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reg clock, in;
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initial begin
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clock = 1;
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forever #1 clock = ~clock;
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end
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integer i;
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localparam [40:0] pattern = 40'hfadf014932;
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initial begin
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for (i = 0; i < 40; i++) begin
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in = pattern[i];
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#2;
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end
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$finish;
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end
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`FOO(A)
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`FOO(B)
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`FOO(C)
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`FOO(D)
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`FOO(E)
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`FOO(F)
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`FOO(G)
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`FOO(H)
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endmodule
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