convert logics with initial values to regs, not wires

2026-08-31 17:54:22 +02:00 · 2021-07-01 23:17:08 -04:00
parent 9de4a3c99c
commit d32c0a1b09
10 changed files with 11 additions and 12 deletions
@@ -1,4 +1,4 @@
 module top;
-    wire [2:0] s = 3'b110;
+    reg [2:0] s = 3'b110;
    initial #1 $display("%b", s);
 endmodule