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convert logics with initial values to regs, not wires

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This commit is contained in:
Zachary Snow
2021-07-01 23:17:08 -04:00
parent 9de4a3c99c
commit d32c0a1b09
10 changed files with 11 additions and 12 deletions
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test/core/struct_integer.v
+1 -1
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@@ -1,4 +1,4 @@
module top;
wire [32*3-1:0] s = {32'd1, 32'd2, 32'd3};
reg [32*3-1:0] s = {32'd1, 32'd2, 32'd3};
initial #1 $display("%b %b %b %b", s, s[64+:32], s[32+:32], s[0+:32]);
endmodule