fix bit param sizing (resolves #94)

src/Convert/Logic.hs

@@ -150,6 +150,8 @@ convertDescription ports orig =
         convertModuleItem other = other
         -- all other logics (i.e. inside of functions) become regs
         convertDecl :: Decl -> Decl
+        convertDecl (Param s (IntegerVector _ sg []) x e) =
+            Param s (Implicit sg [(Number "0", Number "0")]) x e
         convertDecl (Param s (IntegerVector _ sg rs) x e) =
             Param s (Implicit sg rs) x e
         convertDecl (Variable d (IntegerVector TLogic sg rs) x a e) =

test/basic/bit.sv

@@ -0,0 +1,26 @@
+module Example;
+    parameter bit P = 0;
+    initial $display("Example: %b", P);
+endmodule
+
+module top;
+    Example      a();
+    Example #(0) b();
+    Example #(1) c();
+    Example #(2) d();
+    Example #(3) e();
+
+    function bit foo;
+        input bit inp;
+        return inp ^ 1;
+    endfunction
+    initial begin
+        $display("foo(0) = %b", foo(0));
+        $display("foo(1) = %b", foo(1));
+        $display("foo(2) = %b", foo(2));
+        $display("foo(3) = %b", foo(3));
+    end
+
+    bit x;
+    assign x = 1;
+endmodule

test/basic/bit.v

@@ -0,0 +1,26 @@
+module Example;
+    parameter [0:0] P = 0;
+    initial $display("Example: %b", P);
+endmodule
+
+module top;
+    Example      a();
+    Example #(0) b();
+    Example #(1) c();
+    Example #(2) d();
+    Example #(3) e();
+
+    function [0:0] foo;
+        input [0:0] inp;
+        foo = inp ^ 1;
+    endfunction
+    initial begin
+        $display("foo(0) = %b", foo(0));
+        $display("foo(1) = %b", foo(1));
+        $display("foo(2) = %b", foo(2));
+        $display("foo(3) = %b", foo(3));
+    end
+
+    wire x;
+    assign x = 1;
+endmodule