From cbe0071e43cc7176bc58748f91241b4e9cc1c32a Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Sun, 14 Jun 2020 19:45:32 -0400 Subject: [PATCH] fix bit param sizing (resolves #94) --- src/Convert/Logic.hs | 2 ++ test/basic/bit.sv | 26 ++++++++++++++++++++++++++ test/basic/bit.v | 26 ++++++++++++++++++++++++++ 3 files changed, 54 insertions(+) create mode 100644 test/basic/bit.sv create mode 100644 test/basic/bit.v diff --git a/src/Convert/Logic.hs b/src/Convert/Logic.hs index 5d9e0c4..7296c33 100644 --- a/src/Convert/Logic.hs +++ b/src/Convert/Logic.hs @@ -150,6 +150,8 @@ convertDescription ports orig = convertModuleItem other = other -- all other logics (i.e. inside of functions) become regs convertDecl :: Decl -> Decl + convertDecl (Param s (IntegerVector _ sg []) x e) = + Param s (Implicit sg [(Number "0", Number "0")]) x e convertDecl (Param s (IntegerVector _ sg rs) x e) = Param s (Implicit sg rs) x e convertDecl (Variable d (IntegerVector TLogic sg rs) x a e) = diff --git a/test/basic/bit.sv b/test/basic/bit.sv new file mode 100644 index 0000000..abfb688 --- /dev/null +++ b/test/basic/bit.sv @@ -0,0 +1,26 @@ +module Example; + parameter bit P = 0; + initial $display("Example: %b", P); +endmodule + +module top; + Example a(); + Example #(0) b(); + Example #(1) c(); + Example #(2) d(); + Example #(3) e(); + + function bit foo; + input bit inp; + return inp ^ 1; + endfunction + initial begin + $display("foo(0) = %b", foo(0)); + $display("foo(1) = %b", foo(1)); + $display("foo(2) = %b", foo(2)); + $display("foo(3) = %b", foo(3)); + end + + bit x; + assign x = 1; +endmodule diff --git a/test/basic/bit.v b/test/basic/bit.v new file mode 100644 index 0000000..8a3a1b6 --- /dev/null +++ b/test/basic/bit.v @@ -0,0 +1,26 @@ +module Example; + parameter [0:0] P = 0; + initial $display("Example: %b", P); +endmodule + +module top; + Example a(); + Example #(0) b(); + Example #(1) c(); + Example #(2) d(); + Example #(3) e(); + + function [0:0] foo; + input [0:0] inp; + foo = inp ^ 1; + endfunction + initial begin + $display("foo(0) = %b", foo(0)); + $display("foo(1) = %b", foo(1)); + $display("foo(2) = %b", foo(2)); + $display("foo(3) = %b", foo(3)); + end + + wire x; + assign x = 1; +endmodule