initial support for system tasks

src/Convert.hs

@@ -51,6 +51,7 @@ import qualified Convert.StringParam
 import qualified Convert.StringType
 import qualified Convert.Struct
 import qualified Convert.StructConst
+import qualified Convert.SystemTasks
 import qualified Convert.TFBlock
 import qualified Convert.Typedef
 import qualified Convert.TypeOf
@@ -121,6 +122,7 @@ initialPhases tops selectExclude =
     , Convert.Interface.disambiguate
     , Convert.Package.convert
     , Convert.StructConst.convert
+    , Convert.SystemTasks.convert
     , Convert.PortDecl.convert
     , Convert.ParamNoDefault.convert tops
     , Convert.ResolveBindings.convert

src/Convert/SystemTasks.hs

@@ -0,0 +1,49 @@
+{- sv2v
+- Author: Ethan Sifferman <ethan@sifferman.dev>
+-
+- Conversion of SystemVerilog System Tasks to Verilog.
+-}
+
+module Convert.SystemTasks (convert) where
+
+import Convert.Traverse
+import Language.SystemVerilog.AST
+
+convert :: [AST] -> [AST]
+convert =
+    map $ traverseDescriptions $ traverseModuleItems $
+    traverseStmts $ traverseNestedStmts convertStmt
+
+convertStmt :: Stmt -> Stmt
+convertStmt (Subroutine (Ident "$info") args) =
+    Block Seq "" [] [
+        (Subroutine (Ident "$write") (Args [(String "[%0t] Info: "), (Call (Ident "$time") (Args [] []))] [])),
+        (Subroutine (Ident "$display") args)
+    ]
+
+convertStmt (Subroutine (Ident "$warning") args) =
+    Block Seq "" [] [
+        (Subroutine (Ident "$write") (Args [(String "[%0t] Warning: "), (Call (Ident "$time") (Args [] []))] [])),
+        (Subroutine (Ident "$display") args)
+    ]
+
+convertStmt (Subroutine (Ident "$error") args) =
+    Block Seq "" [] [
+        (Subroutine (Ident "$write") (Args [(String "[%0t] Error: "), (Call (Ident "$time") (Args [] []))] [])),
+        (Subroutine (Ident "$display") args)
+    ]
+
+convertStmt (Subroutine (Ident "$fatal") (Args [] [])) =
+    Block Seq "" [] [
+        (Subroutine (Ident "$write") (Args [(String "[%0t] Fatal: "), (Call (Ident "$time") (Args [] []))] [])),
+        (Subroutine (Ident "$display") (Args [] [])),
+        (Subroutine (Ident "$finish") (Args [] []))
+    ]
+convertStmt (Subroutine (Ident "$fatal") (Args (finishArgs:displayArgs) [])) =
+    Block Seq "" [] [
+        (Subroutine (Ident "$write") (Args [(String "Fatal:")] [])),
+        (Subroutine (Ident "$display") (Args displayArgs [])),
+        (Subroutine (Ident "$finish") (Args [finishArgs] []))
+    ]
+
+convertStmt other = other

src/Language/SystemVerilog/AST/Expr.hs

@@ -138,6 +138,8 @@ instance Show Expr where
         showString " : " .
         shows f .
         showChar ')'
+    showsPrec _ (Call     e (Args [] [])) =
+        shows e
     showsPrec _ (Call     e l  ) =
         shows e .
         shows l

sv2v.cabal

@@ -104,6 +104,7 @@ executable sv2v
     Convert.StringType
     Convert.Struct
     Convert.StructConst
+    Convert.SystemTasks
     Convert.TFBlock
     Convert.Traverse
     Convert.Typedef

test/nosim/system_tasks.sv

@@ -0,0 +1,12 @@
+module top;
+    initial begin
+        $info;
+        $info("%b", 1);
+        $warning;
+        $warning("%b", 2);
+        $error;
+        $error("%b", 3);
+        $fatal;
+        $fatal(0, "%b", 4);
+    end
+endmodule