visit nested LHSs in enum, typedef, and typeof conversions

CHANGELOG.md

@@ -11,6 +11,8 @@
 * Fixed `--write path/to/dir/` with directives like `` `default_nettype ``
 * Fixed `logic` incorrectly converted to `wire` even when provided to a task or
   function output port
+* Fixed conversion of enum item names and typenames nested deeply within the
+  left-hand side of an assignment
 * Fixed `input signed` ports of interface-using modules producing invalid
   declarations after inlining
 * Fixed `` `resetall `` not resetting the `` `default_nettype ``

src/Convert/Enum.hs

@@ -47,7 +47,7 @@ traverseModuleItemM (Genvar x) =
     insertElem x Nil >> return (Genvar x)
 traverseModuleItemM item =
     traverseNodesM traverseExprM return traverseTypeM traverseLHSM return item
-    where traverseLHSM = traverseLHSExprsM traverseExprM
+    where traverseLHSM = traverseNestedLHSsM $ traverseLHSExprsM traverseExprM
 
 traverseGenItemM :: GenItem -> SC GenItem
 traverseGenItemM = traverseGenItemExprsM traverseExprM

src/Convert/TypeOf.hs

@@ -79,7 +79,7 @@ insertType ident typ = do
 traverseModuleItemM :: ModuleItem -> ST ModuleItem
 traverseModuleItemM =
     traverseNodesM traverseExprM return traverseTypeM traverseLHSM return
-    where traverseLHSM = traverseLHSExprsM traverseExprM
+    where traverseLHSM = traverseNestedLHSsM $ traverseLHSExprsM traverseExprM
 
 -- convert TypeOf in a GenItem
 traverseGenItemM :: GenItem -> ST GenItem

src/Convert/Typedef.hs

@@ -88,7 +88,7 @@ traverseModuleItemM item = traverseModuleItemM' item
 traverseModuleItemM' :: ModuleItem -> SC ModuleItem
 traverseModuleItemM' =
     traverseNodesM traverseExprM return traverseTypeM traverseLHSM return
-    where traverseLHSM = traverseLHSExprsM traverseExprM
+    where traverseLHSM = traverseNestedLHSsM $ traverseLHSExprsM traverseExprM
 
 traverseGenItemM :: GenItem -> SC GenItem
 traverseGenItemM = traverseGenItemExprsM traverseExprM

test/core/typename_lhs_nest.sv

@@ -0,0 +1,12 @@
+module top;
+    logic x;
+    logic [2:0] y;
+    for (genvar i = 0; i < 3; i++) begin : blk
+        wire w;
+        assign y[i] = w;
+    end
+    localparam type T = enum int { K = 0 };
+    assign blk[K].w = 1;
+    assign blk[$bits(x)].w = 1;
+    assign blk[$bits(T) - 30].w = 1;
+endmodule

test/core/typename_lhs_nest.v

@@ -0,0 +1,5 @@
+module top;
+    wire x;
+    wire [2:0] y;
+    assign y = 1'sb1;
+endmodule