mirror of https://github.com/zachjs/sv2v.git
updated binary and unary operator printing (resolves #72)
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@ -75,8 +75,8 @@ instance Show Expr where
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show (Repeat e l ) = printf "{%s {%s}}" (show e) (commas $ map show l)
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show (Repeat e l ) = printf "{%s {%s}}" (show e) (commas $ map show l)
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show (Concat l ) = printf "{%s}" (commas $ map show l)
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show (Concat l ) = printf "{%s}" (commas $ map show l)
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show (Stream o e l) = printf "{%s %s%s}" (show o) (show e) (show $ Concat l)
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show (Stream o e l) = printf "{%s %s%s}" (show o) (show e) (show $ Concat l)
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show (UniOp o e ) = printf "%s%s" (show o) (show e)
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show (UniOp o e ) = printf "%s%s" (show o) (showUniOpPrec e)
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show (BinOp o a b) = printf "(%s %s %s)" (show a) (show o) (show b)
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show (BinOp o a b) = printf "%s %s %s" (showBinOpPrec a) (show o) (showBinOpPrec b)
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show (Dot e n ) = printf "%s.%s" (show e) n
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show (Dot e n ) = printf "%s.%s" (show e) n
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show (Mux c a b) = printf "(%s ? %s : %s)" (show c) (show a) (show b)
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show (Mux c a b) = printf "(%s ? %s : %s)" (show c) (show a) (show b)
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show (Call e l ) = printf "%s%s" (show e) (show l)
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show (Call e l ) = printf "%s%s" (show e) (show l)
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@ -175,6 +175,15 @@ readNumber n =
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'\'' : 'd' : rest -> rest
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'\'' : 'd' : rest -> rest
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_ -> n
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_ -> n
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showUniOpPrec :: Expr -> String
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showUniOpPrec (e @ UniOp{}) = printf "(%s)" (show e)
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showUniOpPrec (e @ BinOp{}) = printf "(%s)" (show e)
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showUniOpPrec e = show e
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showBinOpPrec :: Expr -> String
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showBinOpPrec (e @ BinOp{}) = printf "(%s)" (show e)
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showBinOpPrec e = show e
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-- basic expression simplfication utility to help us generate nicer code in the
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-- basic expression simplfication utility to help us generate nicer code in the
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-- common case of ranges like `[FOO-1:0]`
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-- common case of ranges like `[FOO-1:0]`
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simplify :: Expr -> Expr
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simplify :: Expr -> Expr
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@ -0,0 +1,5 @@
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module Example(a, b);
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input logic [1:0] a;
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output logic b;
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assign b = !(&a);
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endmodule
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@ -0,0 +1,5 @@
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module Example(a, b);
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input wire [1:0] a;
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output wire b;
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assign b = !(&a);
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endmodule
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@ -0,0 +1,12 @@
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module top;
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reg [1:0] a;
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wire b;
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Example example(a, b);
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initial begin
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$monitor("%2d %b %b", $time, a, b);
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#1;
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#1; a[0] = 1;
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#1; a[1] = 1;
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#1; a[0] = 1'sbx;
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end
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endmodule
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