From b124a561f23c247583cfd65948499a462eb22b45 Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Sat, 15 Feb 2020 14:11:09 -0500 Subject: [PATCH] updated binary and unary operator printing (resolves #72) --- src/Language/SystemVerilog/AST/Expr.hs | 13 +++++++++++-- test/basic/uniop_prec.sv | 5 +++++ test/basic/uniop_prec.v | 5 +++++ test/basic/uniop_prec_tb.v | 12 ++++++++++++ 4 files changed, 33 insertions(+), 2 deletions(-) create mode 100644 test/basic/uniop_prec.sv create mode 100644 test/basic/uniop_prec.v create mode 100644 test/basic/uniop_prec_tb.v diff --git a/src/Language/SystemVerilog/AST/Expr.hs b/src/Language/SystemVerilog/AST/Expr.hs index 9a0f5cc..d2a18cd 100644 --- a/src/Language/SystemVerilog/AST/Expr.hs +++ b/src/Language/SystemVerilog/AST/Expr.hs @@ -75,8 +75,8 @@ instance Show Expr where show (Repeat e l ) = printf "{%s {%s}}" (show e) (commas $ map show l) show (Concat l ) = printf "{%s}" (commas $ map show l) show (Stream o e l) = printf "{%s %s%s}" (show o) (show e) (show $ Concat l) - show (UniOp o e ) = printf "%s%s" (show o) (show e) - show (BinOp o a b) = printf "(%s %s %s)" (show a) (show o) (show b) + show (UniOp o e ) = printf "%s%s" (show o) (showUniOpPrec e) + show (BinOp o a b) = printf "%s %s %s" (showBinOpPrec a) (show o) (showBinOpPrec b) show (Dot e n ) = printf "%s.%s" (show e) n show (Mux c a b) = printf "(%s ? %s : %s)" (show c) (show a) (show b) show (Call e l ) = printf "%s%s" (show e) (show l) @@ -175,6 +175,15 @@ readNumber n = '\'' : 'd' : rest -> rest _ -> n +showUniOpPrec :: Expr -> String +showUniOpPrec (e @ UniOp{}) = printf "(%s)" (show e) +showUniOpPrec (e @ BinOp{}) = printf "(%s)" (show e) +showUniOpPrec e = show e + +showBinOpPrec :: Expr -> String +showBinOpPrec (e @ BinOp{}) = printf "(%s)" (show e) +showBinOpPrec e = show e + -- basic expression simplfication utility to help us generate nicer code in the -- common case of ranges like `[FOO-1:0]` simplify :: Expr -> Expr diff --git a/test/basic/uniop_prec.sv b/test/basic/uniop_prec.sv new file mode 100644 index 0000000..427d323 --- /dev/null +++ b/test/basic/uniop_prec.sv @@ -0,0 +1,5 @@ +module Example(a, b); + input logic [1:0] a; + output logic b; + assign b = !(&a); +endmodule diff --git a/test/basic/uniop_prec.v b/test/basic/uniop_prec.v new file mode 100644 index 0000000..58c5e09 --- /dev/null +++ b/test/basic/uniop_prec.v @@ -0,0 +1,5 @@ +module Example(a, b); + input wire [1:0] a; + output wire b; + assign b = !(&a); +endmodule diff --git a/test/basic/uniop_prec_tb.v b/test/basic/uniop_prec_tb.v new file mode 100644 index 0000000..3aeddda --- /dev/null +++ b/test/basic/uniop_prec_tb.v @@ -0,0 +1,12 @@ +module top; + reg [1:0] a; + wire b; + Example example(a, b); + initial begin + $monitor("%2d %b %b", $time, a, b); + #1; + #1; a[0] = 1; + #1; a[1] = 1; + #1; a[0] = 1'sbx; + end +endmodule