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alias macromodule to module

This commit is contained in:
Zachary Snow 2020-02-01 16:45:33 -05:00
parent 1a9068409e
commit a402a73477
1 changed files with 1 additions and 0 deletions
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src/Language/SystemVerilog/Parser/Parse.y
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@ -522,6 +522,7 @@ PartHeader :: { [Attr] -> Bool -> PartKW -> [ModuleItem] -> Description }
ModuleKW :: { PartKW } ModuleKW :: { PartKW }
: "module" { Module } : "module" { Module }
| "macromodule" { Module }
InterfaceKW :: { PartKW } InterfaceKW :: { PartKW }
: "interface" { Interface } : "interface" { Interface }