From a402a7347708ec40c39825435dbff9967a3931e7 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Sat, 1 Feb 2020 16:45:33 -0500
Subject: [PATCH] alias macromodule to module

---
 src/Language/SystemVerilog/Parser/Parse.y | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y
index 21b0f37..8bb3e41 100644
--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -522,6 +522,7 @@ PartHeader :: { [Attr] -> Bool -> PartKW -> [ModuleItem] -> Description }
 
 ModuleKW :: { PartKW }
   : "module" { Module }
+  | "macromodule" { Module }
 InterfaceKW :: { PartKW }
   : "interface" { Interface }