support for delays on continuous assignments

src/Convert/Interface.hs

@@ -177,7 +177,7 @@ inlineInterface (ports, items) (instanceName, instancePorts) =
                 then ports
                 else origInstancePortNames
         portBindings =
-            map (\(ident, Just expr) -> Assign (LHSIdent ident) expr) $
+            map (\(ident, Just expr) -> Assign Nothing (LHSIdent ident) expr) $
             filter (isJust . snd) $
             zip instancePortNames instancePortExprs
 

src/Convert/PackedArray.hs

@@ -167,7 +167,7 @@ unflattener writeToFlatVariant arr (t, (majorHi, majorLo)) =
             [ localparam startBit
                 (simplify $ BinOp Add majorLo
                     (BinOp Mul (Ident index) size))
-            , GenModuleItem $ (uncurry Assign) $
+            , GenModuleItem $ (uncurry $ Assign Nothing) $
                 if not writeToFlatVariant
                     then (LHSBit (LHSIdent arrUnflat) $ Ident index, Range (Ident arr) origRange)
                     else (LHSRange (LHSIdent arr) origRange, Bit (Ident arrUnflat) (Ident index))

src/Convert/Traverse.hs

@@ -301,14 +301,16 @@ traverseExprsM mapper = moduleItemMapper
 
     moduleItemMapper (MIDecl decl) =
         declMapper decl >>= return . MIDecl
-    moduleItemMapper (Assign lhs expr) =
-        exprMapper expr >>= return . Assign lhs
     moduleItemMapper (Defparam lhs expr) =
         exprMapper expr >>= return . Defparam lhs
     moduleItemMapper (AlwaysC kw stmt) =
         stmtMapper stmt >>= return . AlwaysC kw
     moduleItemMapper (Initial stmt) =
         stmtMapper stmt >>= return . Initial
+    moduleItemMapper (Assign delay lhs expr) = do
+        delay' <- maybeExprMapper delay
+        expr' <- exprMapper expr
+        return $ Assign delay' lhs expr'
     moduleItemMapper (MIPackageItem (Function lifetime ret f decls stmts)) = do
         decls' <- mapM declMapper decls
         stmts' <- mapM stmtMapper stmts
@@ -349,9 +351,9 @@ traverseLHSsM :: Monad m => MapperM m LHS -> MapperM m ModuleItem
 traverseLHSsM mapper item =
     traverseStmtsM (traverseStmtLHSsM mapper) item >>= traverseModuleItemLHSsM
     where
-        traverseModuleItemLHSsM (Assign lhs expr) = do
+        traverseModuleItemLHSsM (Assign delay lhs expr) = do
             lhs' <- mapper lhs
-            return $ Assign lhs' expr
+            return $ Assign delay lhs' expr
         traverseModuleItemLHSsM (Defparam lhs expr) = do
             lhs' <- mapper lhs
             return $ Defparam lhs' expr
@@ -496,9 +498,9 @@ traverseAsgnsM mapper = moduleItemMapper
     where
         moduleItemMapper item = miMapperA item >>= miMapperB
 
-        miMapperA (Assign lhs expr) = do
+        miMapperA (Assign delay lhs expr) = do
             (lhs', expr') <- mapper (lhs, expr)
-            return $ Assign lhs' expr'
+            return $ Assign delay lhs' expr'
         miMapperA (Defparam lhs expr) = do
             (lhs', expr') <- mapper (lhs, expr)
             return $ Defparam lhs' expr'

src/Language/SystemVerilog/AST.hs

@@ -111,7 +111,7 @@ instance Show PartKW where
 data ModuleItem
   = MIDecl     Decl
   | AlwaysC    AlwaysKW Stmt
-  | Assign     LHS Expr
+  | Assign     (Maybe Expr) LHS Expr
   | Defparam   LHS Expr
   | Instance   Identifier [PortBinding] Identifier (Maybe Range) [PortBinding]
   | Genvar     Identifier
@@ -143,7 +143,8 @@ instance Show ModuleItem where
   show thing = case thing of
     MIDecl     nest  -> show nest
     AlwaysC    k b   -> printf "%s %s" (show k) (show b)
-    Assign     a b   -> printf "assign %s = %s;" (show a) (show b)
+    Assign     d a b -> printf "assign %s%s = %s;" delayStr (show a) (show b)
+      where delayStr = maybe "" (\e -> "#(" ++ show e ++ ") ") d
     Defparam   a b   -> printf "defparam %s = %s;" (show a) (show b)
     Instance   m params i r ports
       | null params -> printf "%s %s%s%s;"     m                    i rStr (showPorts ports)

src/Language/SystemVerilog/Parser/Parse.y

@@ -396,7 +396,7 @@ ModuleItem :: { [ModuleItem] }
   | "parameter"  ParamType DeclAsgns ";" { map MIDecl $ map (uncurry $ Parameter  $2) $3 }
   | "localparam" ParamType DeclAsgns ";" { map MIDecl $ map (uncurry $ Localparam $2) $3 }
   | "defparam" DefparamAsgns ";"         { map (uncurry Defparam) $2 }
-  | "assign" LHS "=" Expr ";"            { [Assign $2 $4] }
+  | "assign" opt(DelayControl) LHS "=" Expr ";" { [Assign $2 $3 $5] }
   | AlwaysKW Stmt                        { [AlwaysC $1 $2] }
   | "initial" Stmt                       { [Initial $2] }
   | "genvar" Identifiers ";"             { map Genvar $2 }
@@ -554,19 +554,19 @@ DeclOrStmt :: { ([Decl], [Stmt]) }
 
 TimingControl :: { Timing }
   : DelayOrEventControl { $1 }
-  | CycleDelay          { $1 }
+  | CycleDelay          { Cycle $1 }
 DelayOrEventControl :: { Timing }
-  : DelayControl { $1 }
-  | EventControl { $1 }
-DelayControl :: { Timing }
-  : "#" DelayValue   { Delay $2 }
-  | "#" "(" Expr ")" { Delay $3 }
-CycleDelay :: { Timing }
-  : "##" Expr { Cycle $2 }
-EventControl :: { Timing }
-  : "@" "(" Senses ")" { Event $3 }
-  | "@" "(*)"          { Event SenseStar }
-  | "@*"               { Event SenseStar }
+  : DelayControl { Delay $1 }
+  | EventControl { Event $1 }
+DelayControl :: { Expr }
+  : "#" DelayValue   { $2 }
+  | "#" "(" Expr ")" { $3 }
+CycleDelay :: { Expr }
+  : "##" Expr { $2 }
+EventControl :: { Sense }
+  : "@" "(" Senses ")" { $3 }
+  | "@" "(*)"          { SenseStar }
+  | "@*"               { SenseStar }
 Senses :: { Sense }
   : Sense             { $1 }
   | Senses "or" Sense { SenseOr $1 $3 }