module item statement traversals only visit the top level

This commit is contained in:
Zachary Snow 2021-07-15 18:05:47 -04:00
parent 2eee536f62
commit a2b99fa9dd
11 changed files with 25 additions and 19 deletions

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@ -14,7 +14,7 @@ import Language.SystemVerilog.AST
convert :: [AST] -> [AST]
convert =
map $ traverseDescriptions $ traverseModuleItems $
( traverseStmts convertStmt
( traverseStmts (traverseNestedStmts convertStmt)
. traverseGenItems (traverseNestedGenItems convertGenItem)
)

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@ -18,7 +18,8 @@ convertModuleItem (AssertionItem item) =
map (GenModuleItem . MIPackageItem . Decl . CommentDecl) $
"removed an assertion item" :
(lines $ show $ AssertionItem item)
convertModuleItem other = traverseStmts convertStmt other
convertModuleItem other =
traverseStmts (traverseNestedStmts convertStmt) other
convertStmt :: Stmt -> Stmt
convertStmt (Assertion _) = Null

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@ -16,7 +16,7 @@ import Language.SystemVerilog.AST
convert :: [AST] -> [AST]
convert =
map $ traverseDescriptions $ traverseModuleItems
(convertModuleItem . traverseStmts convertStmt)
(convertModuleItem . traverseStmts (traverseNestedStmts convertStmt))
convertModuleItem :: ModuleItem -> ModuleItem
convertModuleItem (MIPackageItem (Function ml t f decls stmts)) =

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@ -17,7 +17,7 @@ import Language.SystemVerilog.AST
convert :: [AST] -> [AST]
convert =
map $ traverseDescriptions $ traverseModuleItems $
traverseStmts convertStmt
traverseStmts $ traverseNestedStmts convertStmt
convertStmt :: Stmt -> Stmt

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@ -16,7 +16,7 @@ import Language.SystemVerilog.AST
convert :: [AST] -> [AST]
convert =
map $ traverseDescriptions $ traverseModuleItems $
traverseStmts convertStmt
traverseStmts $ traverseNestedStmts convertStmt
convertStmt :: Stmt -> Stmt
convertStmt (Foreach x idxs stmt) =

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@ -23,8 +23,11 @@ convert = map $ traverseDescriptions convertDescription
convertDescription :: Description -> Description
convertDescription (description @ Part{}) =
traverseModuleItems (traverseStmts $ convertStmt functions) description
where functions = execWriter $
traverseModuleItems traverseModuleItem description
where
traverseModuleItem =
traverseStmts $ traverseNestedStmts $ convertStmt functions
functions = execWriter $
collectModuleItemsM collectFunctionsM description
convertDescription other = other

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@ -28,7 +28,7 @@ convert = map $ traverseDescriptions $ traverseModuleItems convertModuleItem
convertModuleItem :: ModuleItem -> ModuleItem
convertModuleItem item =
traverseExprs (traverseNestedExprs convertExpr) $
traverseStmts convertStmt $
traverseStmts (traverseNestedStmts convertStmt) $
item
convertExpr :: Expr -> Expr

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@ -29,7 +29,7 @@ convertDescription description =
convertModuleItem :: TFs -> ModuleItem -> ModuleItem
convertModuleItem tfs =
(traverseExprs $ traverseNestedExprs $ convertExpr tfs) .
(traverseStmts $ convertStmt tfs)
(traverseStmts $ traverseNestedStmts $ convertStmt tfs)
collectTF :: ModuleItem -> Writer TFs ()
collectTF (MIPackageItem (Function _ _ f decls _)) = collectTFDecls f decls

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@ -23,7 +23,8 @@ convert asts =
-- we collect all the existing blocks in the first pass to make sure we
-- don't generate conflicting names on repeated passes of this conversion
evalState (runner collectStmtM asts >>= runner traverseStmtM) Set.empty
where runner = mapM . traverseDescriptionsM . traverseModuleItemsM . traverseStmtsM
where runner = mapM . traverseDescriptionsM . traverseModuleItemsM .
traverseStmtsM . traverseNestedStmtsM
collectStmtM :: Stmt -> State Idents Stmt
collectStmtM (Block kw x decls stmts) = do

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@ -185,19 +185,18 @@ traverseStmtsM :: Monad m => MapperM m Stmt -> MapperM m ModuleItem
traverseStmtsM mapper = moduleItemMapper
where
moduleItemMapper (AlwaysC kw stmt) =
fullMapper stmt >>= return . AlwaysC kw
mapper stmt >>= return . AlwaysC kw
moduleItemMapper (MIPackageItem (Function lifetime ret name decls stmts)) = do
stmts' <- mapM fullMapper stmts
stmts' <- mapM mapper stmts
return $ MIPackageItem $ Function lifetime ret name decls stmts'
moduleItemMapper (MIPackageItem (Task lifetime name decls stmts)) = do
stmts' <- mapM fullMapper stmts
stmts' <- mapM mapper stmts
return $ MIPackageItem $ Task lifetime name decls stmts'
moduleItemMapper (Initial stmt) =
fullMapper stmt >>= return . Initial
mapper stmt >>= return . Initial
moduleItemMapper (Final stmt) =
fullMapper stmt >>= return . Final
mapper stmt >>= return . Final
moduleItemMapper other = return $ other
fullMapper = traverseNestedStmtsM mapper
traverseStmts :: Mapper Stmt -> Mapper ModuleItem
traverseStmts = unmonad traverseStmtsM
@ -719,7 +718,8 @@ collectStmtExprsM = collectify traverseStmtExprsM
traverseLHSsM :: Monad m => MapperM m LHS -> MapperM m ModuleItem
traverseLHSsM mapper =
traverseStmtsM (traverseStmtLHSsM mapper) >=> traverseModuleItemLHSsM
traverseStmtsM (traverseNestedStmtsM $ traverseStmtLHSsM mapper)
>=> traverseModuleItemLHSsM
where
traverseModuleItemLHSsM (Assign delay lhs expr) = do
lhs' <- mapper lhs
@ -1055,7 +1055,7 @@ traverseAsgnsM mapper = moduleItemMapper
return $ Defparam lhs' expr'
miMapperA other = return other
miMapperB = traverseStmtsM stmtMapper
miMapperB = traverseStmtsM $ traverseNestedStmtsM stmtMapper
stmtMapper = traverseStmtAsgnsM mapper
traverseAsgns :: Mapper (LHS, Expr) -> Mapper ModuleItem

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@ -15,7 +15,8 @@ import Language.SystemVerilog.AST
convert :: [AST] -> [AST]
convert =
map $ traverseDescriptions $ traverseModuleItems $ traverseStmts convertStmt
map $ traverseDescriptions $ traverseModuleItems $ traverseStmts $
traverseNestedStmts convertStmt
convertStmt :: Stmt -> Stmt
convertStmt (If _ cc s1 s2) =