From a2b99fa9ddec5af70020cba1668ac8b873ece27e Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Thu, 15 Jul 2021 18:05:47 -0400 Subject: [PATCH] module item statement traversals only visit the top level --- src/Convert/AsgnOp.hs | 2 +- src/Convert/Assertion.hs | 3 ++- src/Convert/BlockDecl.hs | 2 +- src/Convert/ForAsgn.hs | 2 +- src/Convert/Foreach.hs | 2 +- src/Convert/FuncRoutine.hs | 7 +++++-- src/Convert/Inside.hs | 2 +- src/Convert/KWArgs.hs | 2 +- src/Convert/NamedBlock.hs | 3 ++- src/Convert/Traverse.hs | 16 ++++++++-------- src/Convert/Unique.hs | 3 ++- 11 files changed, 25 insertions(+), 19 deletions(-) diff --git a/src/Convert/AsgnOp.hs b/src/Convert/AsgnOp.hs index 496f704..5001bfa 100644 --- a/src/Convert/AsgnOp.hs +++ b/src/Convert/AsgnOp.hs @@ -14,7 +14,7 @@ import Language.SystemVerilog.AST convert :: [AST] -> [AST] convert = map $ traverseDescriptions $ traverseModuleItems $ - ( traverseStmts convertStmt + ( traverseStmts (traverseNestedStmts convertStmt) . traverseGenItems (traverseNestedGenItems convertGenItem) ) diff --git a/src/Convert/Assertion.hs b/src/Convert/Assertion.hs index bf750de..61890ac 100644 --- a/src/Convert/Assertion.hs +++ b/src/Convert/Assertion.hs @@ -18,7 +18,8 @@ convertModuleItem (AssertionItem item) = map (GenModuleItem . MIPackageItem . Decl . CommentDecl) $ "removed an assertion item" : (lines $ show $ AssertionItem item) -convertModuleItem other = traverseStmts convertStmt other +convertModuleItem other = + traverseStmts (traverseNestedStmts convertStmt) other convertStmt :: Stmt -> Stmt convertStmt (Assertion _) = Null diff --git a/src/Convert/BlockDecl.hs b/src/Convert/BlockDecl.hs index 5584870..0cb14bb 100644 --- a/src/Convert/BlockDecl.hs +++ b/src/Convert/BlockDecl.hs @@ -16,7 +16,7 @@ import Language.SystemVerilog.AST convert :: [AST] -> [AST] convert = map $ traverseDescriptions $ traverseModuleItems - (convertModuleItem . traverseStmts convertStmt) + (convertModuleItem . traverseStmts (traverseNestedStmts convertStmt)) convertModuleItem :: ModuleItem -> ModuleItem convertModuleItem (MIPackageItem (Function ml t f decls stmts)) = diff --git a/src/Convert/ForAsgn.hs b/src/Convert/ForAsgn.hs index ce0462d..b4179e1 100644 --- a/src/Convert/ForAsgn.hs +++ b/src/Convert/ForAsgn.hs @@ -17,7 +17,7 @@ import Language.SystemVerilog.AST convert :: [AST] -> [AST] convert = map $ traverseDescriptions $ traverseModuleItems $ - traverseStmts convertStmt + traverseStmts $ traverseNestedStmts convertStmt convertStmt :: Stmt -> Stmt diff --git a/src/Convert/Foreach.hs b/src/Convert/Foreach.hs index b04b6ee..1160d3a 100644 --- a/src/Convert/Foreach.hs +++ b/src/Convert/Foreach.hs @@ -16,7 +16,7 @@ import Language.SystemVerilog.AST convert :: [AST] -> [AST] convert = map $ traverseDescriptions $ traverseModuleItems $ - traverseStmts convertStmt + traverseStmts $ traverseNestedStmts convertStmt convertStmt :: Stmt -> Stmt convertStmt (Foreach x idxs stmt) = diff --git a/src/Convert/FuncRoutine.hs b/src/Convert/FuncRoutine.hs index 595c8d4..4d4e5f2 100644 --- a/src/Convert/FuncRoutine.hs +++ b/src/Convert/FuncRoutine.hs @@ -23,8 +23,11 @@ convert = map $ traverseDescriptions convertDescription convertDescription :: Description -> Description convertDescription (description @ Part{}) = - traverseModuleItems (traverseStmts $ convertStmt functions) description - where functions = execWriter $ + traverseModuleItems traverseModuleItem description + where + traverseModuleItem = + traverseStmts $ traverseNestedStmts $ convertStmt functions + functions = execWriter $ collectModuleItemsM collectFunctionsM description convertDescription other = other diff --git a/src/Convert/Inside.hs b/src/Convert/Inside.hs index 2d1221a..6ac4bfd 100644 --- a/src/Convert/Inside.hs +++ b/src/Convert/Inside.hs @@ -28,7 +28,7 @@ convert = map $ traverseDescriptions $ traverseModuleItems convertModuleItem convertModuleItem :: ModuleItem -> ModuleItem convertModuleItem item = traverseExprs (traverseNestedExprs convertExpr) $ - traverseStmts convertStmt $ + traverseStmts (traverseNestedStmts convertStmt) $ item convertExpr :: Expr -> Expr diff --git a/src/Convert/KWArgs.hs b/src/Convert/KWArgs.hs index c357a45..de1785d 100644 --- a/src/Convert/KWArgs.hs +++ b/src/Convert/KWArgs.hs @@ -29,7 +29,7 @@ convertDescription description = convertModuleItem :: TFs -> ModuleItem -> ModuleItem convertModuleItem tfs = (traverseExprs $ traverseNestedExprs $ convertExpr tfs) . - (traverseStmts $ convertStmt tfs) + (traverseStmts $ traverseNestedStmts $ convertStmt tfs) collectTF :: ModuleItem -> Writer TFs () collectTF (MIPackageItem (Function _ _ f decls _)) = collectTFDecls f decls diff --git a/src/Convert/NamedBlock.hs b/src/Convert/NamedBlock.hs index 9a16e27..165b8aa 100644 --- a/src/Convert/NamedBlock.hs +++ b/src/Convert/NamedBlock.hs @@ -23,7 +23,8 @@ convert asts = -- we collect all the existing blocks in the first pass to make sure we -- don't generate conflicting names on repeated passes of this conversion evalState (runner collectStmtM asts >>= runner traverseStmtM) Set.empty - where runner = mapM . traverseDescriptionsM . traverseModuleItemsM . traverseStmtsM + where runner = mapM . traverseDescriptionsM . traverseModuleItemsM . + traverseStmtsM . traverseNestedStmtsM collectStmtM :: Stmt -> State Idents Stmt collectStmtM (Block kw x decls stmts) = do diff --git a/src/Convert/Traverse.hs b/src/Convert/Traverse.hs index 79f5c7f..f7f3204 100644 --- a/src/Convert/Traverse.hs +++ b/src/Convert/Traverse.hs @@ -185,19 +185,18 @@ traverseStmtsM :: Monad m => MapperM m Stmt -> MapperM m ModuleItem traverseStmtsM mapper = moduleItemMapper where moduleItemMapper (AlwaysC kw stmt) = - fullMapper stmt >>= return . AlwaysC kw + mapper stmt >>= return . AlwaysC kw moduleItemMapper (MIPackageItem (Function lifetime ret name decls stmts)) = do - stmts' <- mapM fullMapper stmts + stmts' <- mapM mapper stmts return $ MIPackageItem $ Function lifetime ret name decls stmts' moduleItemMapper (MIPackageItem (Task lifetime name decls stmts)) = do - stmts' <- mapM fullMapper stmts + stmts' <- mapM mapper stmts return $ MIPackageItem $ Task lifetime name decls stmts' moduleItemMapper (Initial stmt) = - fullMapper stmt >>= return . Initial + mapper stmt >>= return . Initial moduleItemMapper (Final stmt) = - fullMapper stmt >>= return . Final + mapper stmt >>= return . Final moduleItemMapper other = return $ other - fullMapper = traverseNestedStmtsM mapper traverseStmts :: Mapper Stmt -> Mapper ModuleItem traverseStmts = unmonad traverseStmtsM @@ -719,7 +718,8 @@ collectStmtExprsM = collectify traverseStmtExprsM traverseLHSsM :: Monad m => MapperM m LHS -> MapperM m ModuleItem traverseLHSsM mapper = - traverseStmtsM (traverseStmtLHSsM mapper) >=> traverseModuleItemLHSsM + traverseStmtsM (traverseNestedStmtsM $ traverseStmtLHSsM mapper) + >=> traverseModuleItemLHSsM where traverseModuleItemLHSsM (Assign delay lhs expr) = do lhs' <- mapper lhs @@ -1055,7 +1055,7 @@ traverseAsgnsM mapper = moduleItemMapper return $ Defparam lhs' expr' miMapperA other = return other - miMapperB = traverseStmtsM stmtMapper + miMapperB = traverseStmtsM $ traverseNestedStmtsM stmtMapper stmtMapper = traverseStmtAsgnsM mapper traverseAsgns :: Mapper (LHS, Expr) -> Mapper ModuleItem diff --git a/src/Convert/Unique.hs b/src/Convert/Unique.hs index 65d85ae..e39eceb 100644 --- a/src/Convert/Unique.hs +++ b/src/Convert/Unique.hs @@ -15,7 +15,8 @@ import Language.SystemVerilog.AST convert :: [AST] -> [AST] convert = - map $ traverseDescriptions $ traverseModuleItems $ traverseStmts convertStmt + map $ traverseDescriptions $ traverseModuleItems $ traverseStmts $ + traverseNestedStmts convertStmt convertStmt :: Stmt -> Stmt convertStmt (If _ cc s1 s2) =