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update alignment

This commit is contained in:
Zachary Snow 2025-11-01 22:31:58 -04:00
parent d2428494fb
commit 96469b7bbd
2 changed files with 14 additions and 14 deletions
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14
src/Language/SystemVerilog/AST/ModuleItem.hs
View File

@ -124,14 +124,14 @@ data NInputGateKW
deriving Eq
instance Show NInputGateKW where
show GateAnd = "and"
show GateBufif0 = "bufif0"
show GateNand = "nand"
show GateOr = "or"
show GateNor = "nor"
show GateAnd = "and"
show GateBufif0 = "bufif0"
show GateNand = "nand"
show GateOr = "or"
show GateNor = "nor"
show GateRpmos = "rpmos"
show GateXor = "xor"
show GateXnor = "xnor"
show GateXor = "xor"
show GateXnor = "xnor"
data NOutputGateKW
= GateBuf

14
src/Language/SystemVerilog/Parser/Parse.y
View File

@ -872,14 +872,14 @@ OptGateName :: { (Identifier, [Range]) }
| {- empty -} { ("", []) }
NInputGateKW :: { NInputGateKW }
: "and" { GateAnd }
: "and" { GateAnd }
| "bufif0" { GateBufif0 }
| "nand" { GateNand }
| "or" { GateOr }
| "nor" { GateNor }
| "rpmos" { GateRpmos }
| "xor" { GateXor }
| "xnor" { GateXnor }
| "nand" { GateNand }
| "or" { GateOr }
| "nor" { GateNor }
| "rpmos" { GateRpmos }
| "xor" { GateXor }
| "xnor" { GateXnor }
NOutputGateKW :: { NOutputGateKW }
: "buf" { GateBuf }
| "not" { GateNot }