From 96469b7bbdfe39a1fed64105a2192e16cd0f7034 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Sat, 1 Nov 2025 22:31:58 -0400
Subject: [PATCH] update alignment

---
 src/Language/SystemVerilog/AST/ModuleItem.hs | 14 +++++++-------
 src/Language/SystemVerilog/Parser/Parse.y    | 14 +++++++-------
 2 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/src/Language/SystemVerilog/AST/ModuleItem.hs b/src/Language/SystemVerilog/AST/ModuleItem.hs
index d1a6fdf..8656eba 100644
--- a/src/Language/SystemVerilog/AST/ModuleItem.hs
+++ b/src/Language/SystemVerilog/AST/ModuleItem.hs
@@ -124,14 +124,14 @@ data NInputGateKW
     deriving Eq
 
 instance Show NInputGateKW where
-    show GateAnd  = "and"
-    show GateBufif0  = "bufif0"
-    show GateNand = "nand"
-    show GateOr   = "or"
-    show GateNor  = "nor"
+    show GateAnd    = "and"
+    show GateBufif0 = "bufif0"
+    show GateNand   = "nand"
+    show GateOr     = "or"
+    show GateNor    = "nor"
     show GateRpmos  = "rpmos"
-    show GateXor  = "xor"
-    show GateXnor = "xnor"
+    show GateXor    = "xor"
+    show GateXnor   = "xnor"
 
 data NOutputGateKW
     = GateBuf
diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y
index 637dda3..b6fc7e7 100644
--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -872,14 +872,14 @@ OptGateName :: { (Identifier, [Range]) }
   | {- empty -} { ("", []) }
 
 NInputGateKW :: { NInputGateKW }
-  : "and"  { GateAnd  }
+  : "and"    { GateAnd    }
   | "bufif0" { GateBufif0 }
-  | "nand" { GateNand }
-  | "or"   { GateOr   }
-  | "nor"  { GateNor  }
-  | "rpmos" { GateRpmos }
-  | "xor"  { GateXor  }
-  | "xnor" { GateXnor }
+  | "nand"   { GateNand   }
+  | "or"     { GateOr     }
+  | "nor"    { GateNor    }
+  | "rpmos"  { GateRpmos  }
+  | "xor"    { GateXor    }
+  | "xnor"   { GateXnor   }
 NOutputGateKW :: { NOutputGateKW }
   : "buf"  { GateBuf  }
   | "not"  { GateNot  }