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allow parens around senses

This commit is contained in:
Zachary Snow 2019-10-09 21:41:14 -04:00
parent d2976170f3
commit 910282fbf7
1 changed files with 6 additions and 3 deletions
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9
src/Language/SystemVerilog/Parser/Parse.y
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@ -1015,9 +1015,12 @@ Senses :: { Sense }
| Senses "or" Sense { SenseOr $1 $3 }
| Senses "," Sense { SenseOr $1 $3 }
Sense :: { Sense }
: LHS { Sense $1 }
| "posedge" LHS { SensePosedge $2 }
| "negedge" LHS { SenseNegedge $2 }
: "(" Sense ")" { $2 }
| LHS { Sense $1 }
| "posedge" LHS { SensePosedge $2 }
| "negedge" LHS { SenseNegedge $2 }
| "posedge" "(" LHS ")" { SensePosedge $3 }
| "negedge" "(" LHS ")" { SenseNegedge $3 }
DelayValue :: { Expr }
: Number { Number $1 }