From 910282fbf7eb3e6e8070d3aa39b65be14da67ab9 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Wed, 9 Oct 2019 21:41:14 -0400
Subject: [PATCH] allow parens around senses

---
 src/Language/SystemVerilog/Parser/Parse.y | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y
index 75c76f1..cd60bb5 100644
--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -1015,9 +1015,12 @@ Senses :: { Sense }
   | Senses "or" Sense { SenseOr $1 $3 }
   | Senses ","  Sense { SenseOr $1 $3 }
 Sense :: { Sense }
-  :           LHS { Sense        $1 }
-  | "posedge" LHS { SensePosedge $2 }
-  | "negedge" LHS { SenseNegedge $2 }
+  : "(" Sense ")"         {              $2 }
+  |               LHS     { Sense        $1 }
+  | "posedge"     LHS     { SensePosedge $2 }
+  | "negedge"     LHS     { SenseNegedge $2 }
+  | "posedge" "(" LHS ")" { SensePosedge $3 }
+  | "negedge" "(" LHS ")" { SenseNegedge $3 }
 
 DelayValue :: { Expr }
   : Number { Number $1 }