support for empty port connections

src/Language/SystemVerilog/Parser/Parse.y

@@ -965,11 +965,14 @@ LHSs :: { [LHS] }
   | LHSs "," LHS  { $1 ++ [$3] }
 
 PortBindings :: { [PortBinding] }
-  : "("                    ")" { [] }
-  | "(" PortBindingsInside ")" {% checkPortBindings $2 }
+  : "(" PortBindingsInside ")" {% checkPortBindings $2 }
 PortBindingsInside :: { [PortBinding] }
-  : PortBinding opt(",")               { [$1] }
-  | PortBinding "," PortBindingsInside { $1 : $3}
+  : OptPortBinding                        { [$1] }
+  | OptPortBinding "," PortBindingsInside { $1 : $3}
+OptPortBinding :: { PortBinding }
+  : {- empty -} { ("", Nil) }
+  | PortBinding { $1 }
+
 PortBinding :: { PortBinding }
   : "." Identifier "(" ExprOrNil ")" { ($2, $4) }
   | "." Identifier                   { ($2, Ident $2) }
@@ -1507,7 +1510,12 @@ missingToken expected = do
   throwError $ show p ++ ": Parse error: missing expected `" ++ expected ++ "`"
 
 checkPortBindings :: [PortBinding] -> ParseState [PortBinding]
-checkPortBindings = checkBindings "port connections"
+checkPortBindings [] = return []
+checkPortBindings bindings =
+  checkBindings "port connections" $
+  if last bindings == ("", Nil)
+    then init bindings
+    else bindings
 
 checkParamBindings :: [ParamBinding] -> ParseState [ParamBinding]
 checkParamBindings = checkBindings "parameter overrides"

test/basic/unbound_port.sv

@@ -0,0 +1,29 @@
+`ifndef TRAIL
+`define TRAIL ,
+`endif
+
+module mod #(
+    parameter [23:0] KEY = "INV"
+) (a, b, c);
+    input wire [31:0] a, b, c;
+    initial #1 $display("%s a=%0d b=%0d c=%0d", KEY, a, b, c);
+endmodule
+
+module top;
+    mod #("MA0") MA0(, , );
+    mod #("MA1") MA1(1, , );
+    mod #("MA2") MA2(1, 2, );
+    mod #("MA3") MA3(1, 2, 3);
+    mod #("MA4") MA4(1, , 3);
+    mod #("MA5") MA5(1, , 3);
+    mod #("MA6") MA6(, 2, 3);
+    mod #("MA7") MA7(, , 3);
+    mod #("MB0") MB0(, , `TRAIL);
+    mod #("MB1") MB1(1, , `TRAIL);
+    mod #("MB2") MB2(1, 2, `TRAIL);
+    mod #("MB3") MB3(1, 2, 3 `TRAIL);
+    mod #("MB4") MB4(1, , 3 `TRAIL);
+    mod #("MB5") MB5(1, , 3 `TRAIL);
+    mod #("MB6") MB6(, 2, 3 `TRAIL);
+    mod #("MB7") MB7(, , 3 `TRAIL);
+endmodule

test/basic/unbound_port.v

@@ -0,0 +1,2 @@
+`define TRAIL
+`include "unbound_port.sv"

test/lib/functions.sh

@@ -22,6 +22,7 @@ simulate() {
         -Wall \
         -Wno-select-range \
         -Wno-anachronisms \
+        -Wno-portbind \
         -o $sim_prog \
         -g2005 \
         -DTEST_VCD="\"$sim_vcd\"" \