From 801955ffab6ce4d89e1a274aeb34ffce6a771e21 Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Fri, 21 May 2021 14:02:29 -0400 Subject: [PATCH] support for empty port connections --- src/Language/SystemVerilog/Parser/Parse.y | 18 ++++++++++---- test/basic/unbound_port.sv | 29 +++++++++++++++++++++++ test/basic/unbound_port.v | 2 ++ test/lib/functions.sh | 1 + 4 files changed, 45 insertions(+), 5 deletions(-) create mode 100644 test/basic/unbound_port.sv create mode 100644 test/basic/unbound_port.v diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y index fe6be82..2e58ff7 100644 --- a/src/Language/SystemVerilog/Parser/Parse.y +++ b/src/Language/SystemVerilog/Parser/Parse.y @@ -965,11 +965,14 @@ LHSs :: { [LHS] } | LHSs "," LHS { $1 ++ [$3] } PortBindings :: { [PortBinding] } - : "(" ")" { [] } - | "(" PortBindingsInside ")" {% checkPortBindings $2 } + : "(" PortBindingsInside ")" {% checkPortBindings $2 } PortBindingsInside :: { [PortBinding] } - : PortBinding opt(",") { [$1] } - | PortBinding "," PortBindingsInside { $1 : $3} + : OptPortBinding { [$1] } + | OptPortBinding "," PortBindingsInside { $1 : $3} +OptPortBinding :: { PortBinding } + : {- empty -} { ("", Nil) } + | PortBinding { $1 } + PortBinding :: { PortBinding } : "." Identifier "(" ExprOrNil ")" { ($2, $4) } | "." Identifier { ($2, Ident $2) } @@ -1507,7 +1510,12 @@ missingToken expected = do throwError $ show p ++ ": Parse error: missing expected `" ++ expected ++ "`" checkPortBindings :: [PortBinding] -> ParseState [PortBinding] -checkPortBindings = checkBindings "port connections" +checkPortBindings [] = return [] +checkPortBindings bindings = + checkBindings "port connections" $ + if last bindings == ("", Nil) + then init bindings + else bindings checkParamBindings :: [ParamBinding] -> ParseState [ParamBinding] checkParamBindings = checkBindings "parameter overrides" diff --git a/test/basic/unbound_port.sv b/test/basic/unbound_port.sv new file mode 100644 index 0000000..9226720 --- /dev/null +++ b/test/basic/unbound_port.sv @@ -0,0 +1,29 @@ +`ifndef TRAIL +`define TRAIL , +`endif + +module mod #( + parameter [23:0] KEY = "INV" +) (a, b, c); + input wire [31:0] a, b, c; + initial #1 $display("%s a=%0d b=%0d c=%0d", KEY, a, b, c); +endmodule + +module top; + mod #("MA0") MA0(, , ); + mod #("MA1") MA1(1, , ); + mod #("MA2") MA2(1, 2, ); + mod #("MA3") MA3(1, 2, 3); + mod #("MA4") MA4(1, , 3); + mod #("MA5") MA5(1, , 3); + mod #("MA6") MA6(, 2, 3); + mod #("MA7") MA7(, , 3); + mod #("MB0") MB0(, , `TRAIL); + mod #("MB1") MB1(1, , `TRAIL); + mod #("MB2") MB2(1, 2, `TRAIL); + mod #("MB3") MB3(1, 2, 3 `TRAIL); + mod #("MB4") MB4(1, , 3 `TRAIL); + mod #("MB5") MB5(1, , 3 `TRAIL); + mod #("MB6") MB6(, 2, 3 `TRAIL); + mod #("MB7") MB7(, , 3 `TRAIL); +endmodule diff --git a/test/basic/unbound_port.v b/test/basic/unbound_port.v new file mode 100644 index 0000000..a731db9 --- /dev/null +++ b/test/basic/unbound_port.v @@ -0,0 +1,2 @@ +`define TRAIL +`include "unbound_port.sv" diff --git a/test/lib/functions.sh b/test/lib/functions.sh index e03eabf..8918418 100644 --- a/test/lib/functions.sh +++ b/test/lib/functions.sh @@ -22,6 +22,7 @@ simulate() { -Wall \ -Wno-select-range \ -Wno-anachronisms \ + -Wno-portbind \ -o $sim_prog \ -g2005 \ -DTEST_VCD="\"$sim_vcd\"" \