logic conversion notices procedural assignments in tasks and functions

This commit is contained in:
Zachary Snow
2020-06-25 09:31:39 -07:00
parent 24071d74ac
commit 80154feb5e
3 changed files with 38 additions and 0 deletions
+16
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module top;
logic x, y, z;
task t;
x = 1;
endtask
function f;
y = 1;
f = 0;
endfunction
assign z = 0;
initial begin
t;
$display("%b %b %b %b", x, y, z, f());
$display("%b %b %b %b", x, y, z, f());
end
endmodule
+20
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module top;
reg x, y;
wire z;
task t;
x = 1;
endtask
function f;
input x;
begin
y = 1;
f = 0;
end
endfunction
assign z = 0;
initial begin
t;
$display("%b %b %b %b", x, y, z, f(0));
$display("%b %b %b %b", x, y, z, f(0));
end
endmodule