mirror of https://github.com/zachjs/sv2v.git
logic conversion notices procedural assignments in tasks and functions
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@ -171,6 +171,8 @@ regIdents :: ModuleItem -> Writer Idents ()
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regIdents (item @ AlwaysC{}) = regIdents' item
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regIdents (item @ Initial{}) = regIdents' item
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regIdents (item @ Final{}) = regIdents' item
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regIdents (item @ (MIPackageItem Task {})) = regIdents' item
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regIdents (item @ (MIPackageItem Function{})) = regIdents' item
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regIdents _ = return ()
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regIdents' :: ModuleItem -> Writer Idents ()
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@ -0,0 +1,16 @@
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module top;
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logic x, y, z;
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task t;
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x = 1;
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endtask
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function f;
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y = 1;
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f = 0;
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endfunction
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assign z = 0;
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initial begin
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t;
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$display("%b %b %b %b", x, y, z, f());
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$display("%b %b %b %b", x, y, z, f());
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end
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endmodule
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@ -0,0 +1,20 @@
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module top;
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reg x, y;
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wire z;
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task t;
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x = 1;
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endtask
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function f;
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input x;
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begin
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y = 1;
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f = 0;
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end
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endfunction
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assign z = 0;
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initial begin
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t;
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$display("%b %b %b %b", x, y, z, f(0));
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$display("%b %b %b %b", x, y, z, f(0));
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end
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endmodule
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