logic conversion handles shadowing

test/basic/output_bound_reg.sv

@@ -0,0 +1,37 @@
+module Flip(x, y);
+    input x;
+    output y;
+    assign y = ~x;
+endmodule
+
+module Test1(o);
+    output [1:0] o;
+    logic x = 0;
+    for (genvar i = 0; i < 1; ++i) begin
+        Flip flip(x, o[i]);
+    end
+    initial begin
+        integer i = 0;
+    end
+endmodule
+
+module Test2(o);
+    output o;
+    logic x = 0;
+    Flip flip(x, o);
+    initial begin
+        integer o = 0;
+        x = 0;
+    end
+endmodule
+
+module Test3(o);
+    output o;
+    logic [1:0] x;
+    Flip flip(x[0], x[1]);
+    assign o = x[0];
+    initial x[0] = 0;
+    initial begin
+        integer x = 0;
+    end
+endmodule

test/basic/output_bound_reg.v

@@ -0,0 +1,43 @@
+module Flip(x, y);
+    input x;
+    output y;
+    assign y = ~x;
+endmodule
+
+module Test1(o);
+    output [1:0] o;
+    wire x = 0;
+    generate
+        genvar i;
+        for (i = 0; i < 1; i = i + 1) begin
+            Flip flip(x, o[i]);
+        end
+    endgenerate
+    initial begin : blah
+        integer i;
+        i = 0;
+    end
+endmodule
+
+module Test2(o);
+    output o;
+    wire x = 0;
+    Flip flip(x, o);
+    initial begin : blah
+        integer o;
+        o = 0;
+    end
+endmodule
+
+module Test3(o);
+    output o;
+    reg x_0;
+    wire x_1;
+    Flip flip(x_0, x_1);
+    assign o = x_0;
+    initial x_0 = 0;
+    initial begin : blah
+        integer x;
+        x = 0;
+    end
+endmodule

test/basic/output_bound_reg_tb.v

@@ -0,0 +1,8 @@
+module top;
+    wire [1:0] o1;
+    Test1 bar(o1);
+    wire o2;
+    Test2 test2(o2);
+    wire o3;
+    Test3 test3(o3);
+endmodule