fix unbased unsized literals in ternary exprs

src/Convert/UnbasedUnsized.hs

@@ -3,8 +3,9 @@
  -
  - Conversion for unbased, unsized literals ('0, '1, 'z, 'x)
  -
- - We convert the literals to be signed to enable sign extension, and give them
- - a size of 1 and a binary base. These values implicitly cast as desired in
+ - The literals are given a binary base and are made signed to enable sign
+ - extension. In self-determined contexts, the literals are additionally given
+ - an explicit size of 1. This enables the desired implicit casting in
  - Verilog-2005.
  -}
 
@@ -22,9 +23,26 @@ convert =
 digits :: [Char]
 digits = ['0', '1', 'x', 'z', 'X', 'Z']
 
-convertExpr :: Expr -> Expr
-convertExpr (Number ['\'', ch]) =
+literalFor :: String -> Char -> Expr
+literalFor prefix ch =
     if elem ch digits
-        then Number ("1'sb" ++ [ch])
+        then Number (prefix ++ [ch])
         else error $ "unexpected unbased-unsized digit: " ++ [ch]
+
+sizedLiteralFor :: Char -> Expr
+sizedLiteralFor = literalFor "1'sb"
+
+unsizedLiteralFor :: Char -> Expr
+unsizedLiteralFor = literalFor "'sb"
+
+convertExpr :: Expr -> Expr
+convertExpr (Mux cond left right) =
+    Mux cond (convertExprUnsized left) (convertExprUnsized right)
+convertExpr (Number ['\'', ch]) =
+    sizedLiteralFor ch
 convertExpr other = other
+
+convertExprUnsized :: Expr -> Expr
+convertExprUnsized (Number ['\'', ch]) =
+    unsizedLiteralFor ch
+convertExprUnsized other = other

test/basic/unbased_unsized.sv

@@ -7,4 +7,20 @@ module top;
     `TEST(0);
     `TEST(x);
     `TEST(z);
+
+    logic flag;
+    logic [31:0] i;
+    logic [31:0] a;
+    logic [31:0] b;
+    logic [31:0] c;
+    initial begin
+        i = 42;
+        flag = 1;
+        a = (flag ? '1 : i);
+        b = (flag ? 1'sb1 : i);
+        c = (flag ? '1 : '0);
+        $display("%b", a);
+        $display("%b", b);
+        $display("%b", c);
+    end
 endmodule

test/basic/unbased_unsized.v

@@ -7,4 +7,20 @@ module top;
     `TEST(0)
     `TEST(x)
     `TEST(z)
+
+    reg flag;
+    reg [31:0] i;
+    reg [31:0] a;
+    reg [31:0] b;
+    reg [31:0] c;
+    initial begin
+        i = 42;
+        flag = 1;
+        a = (flag ? 32'hFFFFFFFF : i);
+        b = (flag ? 1'sb1 : i);
+        c = (flag ?  32'hFFFFFFFF: i);
+        $display("%b", a);
+        $display("%b", b);
+        $display("%b", c);
+    end
 endmodule