mirror of https://github.com/zachjs/sv2v.git
starting work to clean up and segment AST
This commit is contained in:
Zachary Snow
parent
cecd141e57
commit
77f0d23d4b
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@ -30,7 +30,7 @@ convertStmt other = other
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lhsToExpr :: LHS -> Expr
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lhsToExpr :: LHS -> Expr
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lhsToExpr (LHSIdent x) = Ident x
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lhsToExpr (LHSIdent x) = Ident x
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lhsToExpr (LHSBit l e) = Bit (lhsToExpr l) e
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lhsToExpr (LHSBit l e) = Bit (lhsToExpr l) e
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lhsToExpr (LHSRange l r) = Range (lhsToExpr l) r
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lhsToExpr (LHSRange l r) = Range (lhsToExpr l) r
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lhsToExpr (LHSDot l x) = Access (lhsToExpr l) x
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lhsToExpr (LHSDot l x) = Dot (lhsToExpr l) x
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lhsToExpr (LHSConcat ls) = Concat $ map lhsToExpr ls
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lhsToExpr (LHSConcat ls) = Concat $ map lhsToExpr ls
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@ -83,7 +83,7 @@ convertDescription interfaces (Part Module name ports items) =
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mapInterface other = other
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mapInterface other = other
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expandPortBinding :: PortBinding -> [PortBinding]
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expandPortBinding :: PortBinding -> [PortBinding]
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expandPortBinding (origBinding @ (portName, Just (Access (Ident instanceName) modportName))) =
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expandPortBinding (origBinding @ (portName, Just (Dot (Ident instanceName) modportName))) =
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case Map.lookup instanceName instances of
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case Map.lookup instanceName instances of
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Nothing -> [origBinding]
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Nothing -> [origBinding]
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Just interfaceName ->
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Just interfaceName ->
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@ -108,7 +108,7 @@ convertDescription interfaces (Part Module name ports items) =
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collectModport _ = return ()
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collectModport _ = return ()
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convertExpr :: Expr -> Expr
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convertExpr :: Expr -> Expr
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convertExpr (orig @ (Access (Ident x) y)) =
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convertExpr (orig @ (Dot (Ident x) y)) =
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if Map.member x modports
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if Map.member x modports
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then Ident (x ++ "_" ++ y)
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then Ident (x ++ "_" ++ y)
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else orig
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else orig
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@ -193,13 +193,13 @@ convertAsgn structs types (lhs, expr) =
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case Map.lookup x types of
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case Map.lookup x types of
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Nothing -> (Implicit Unspecified [], Ident x)
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Nothing -> (Implicit Unspecified [], Ident x)
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Just t -> (t, Ident x)
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Just t -> (t, Ident x)
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convertSubExpr (Access e x) =
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convertSubExpr (Dot e x) =
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case subExprType of
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case subExprType of
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Struct _ _ _ ->
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Struct _ _ _ ->
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if Map.notMember structTf structs
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if Map.notMember structTf structs
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then (fieldType, Access e' x)
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then (fieldType, Dot e' x)
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else (fieldType, Range e' r)
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else (fieldType, Range e' r)
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_ -> (Implicit Unspecified [], Access e' x)
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_ -> (Implicit Unspecified [], Dot e' x)
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where
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where
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(subExprType, e') = convertSubExpr e
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(subExprType, e') = convertSubExpr e
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Struct p fields [] = subExprType
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Struct p fields [] = subExprType
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@ -193,10 +193,9 @@ traverseNestedExprsM mapper = exprMapper
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maybeExprMapper Nothing = return Nothing
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maybeExprMapper Nothing = return Nothing
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maybeExprMapper (Just e) =
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maybeExprMapper (Just e) =
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exprMapper e >>= return . Just
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exprMapper e >>= return . Just
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em (String s) = return $ String s
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em (String s) = return $ String s
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em (Number s) = return $ Number s
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em (Number s) = return $ Number s
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em (ConstBool b) = return $ ConstBool b
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em (Ident i) = return $ Ident i
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em (Ident i) = return $ Ident i
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em (Range e (e1, e2)) = do
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em (Range e (e1, e2)) = do
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e' <- exprMapper e
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e' <- exprMapper e
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e1' <- exprMapper e1
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e1' <- exprMapper e1
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@ -227,8 +226,8 @@ traverseNestedExprsM mapper = exprMapper
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return $ Mux e1' e2' e3'
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return $ Mux e1' e2' e3'
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em (Cast t e) =
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em (Cast t e) =
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exprMapper e >>= return . Cast t
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exprMapper e >>= return . Cast t
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em (Access e x) =
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em (Dot e x) =
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exprMapper e >>= \e' -> return $ Access e' x
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exprMapper e >>= \e' -> return $ Dot e' x
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em (Pattern l) = do
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em (Pattern l) = do
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let names = map fst l
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let names = map fst l
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exprs <- mapM exprMapper $ map snd l
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exprs <- mapM exprMapper $ map snd l
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@ -1,61 +1,64 @@
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{-# LANGUAGE FlexibleInstances #-}
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{- sv2v
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module Language.SystemVerilog.AST
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- Author: Zachary Snow <zach@zachjs.com>
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( Identifier
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- Initial Verilog AST Author: Tom Hawkins <tomahawkins@gmail.com>
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, Description(..)
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-
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, PackageItem(..)
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- This AST allows for the representation of many syntactically invalid things,
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, ModuleItem (..)
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- like input regs or modport declarations inside a module. Representing only
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, Direction (..)
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- syntactically valid files would make working with the AST a nightmare. We
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, Type (..)
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- have placed an emphasis on making the conversion procedures in this project
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, Stmt (..)
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- more easier to write, interpret, and maintain.
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, LHS (..)
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-
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, Expr (..)
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- In the future, we may want to have a utility which performs some basic
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, UniOp (..)
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- invariant checks. I want to avoid making a full type-checker though, as we
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, BinOp (..)
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- should only be given valid SystemVerilog input files.
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, AsgnOp (..)
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-}
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, Sense (..)
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, Timing (..)
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, GenItem (..)
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, AlwaysKW (..)
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, CaseKW (..)
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, PartKW (..)
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, Decl (..)
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, Lifetime (..)
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, NInputGateKW (..)
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, NOutputGateKW (..)
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, AST
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, PortBinding
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, ModportDecl
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, Case
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, Range
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, GenCase
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, typeRanges
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, simplify
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, rangeSize
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, Signing (..)
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, NetType (..)
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, IntegerVectorType (..)
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, IntegerAtomType (..)
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, NonIntegerType (..)
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, Packing (..)
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) where
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import Data.List
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module Language.SystemVerilog.AST
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import Data.Maybe
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( Description(..)
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import Text.Printf
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, PackageItem(..)
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, ModuleItem (..)
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, Direction (..)
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, Stmt (..)
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, LHS (..)
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, Expr (..)
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, Sense (..)
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, Timing (..)
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, GenItem (..)
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, AlwaysKW (..)
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, CaseKW (..)
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, PartKW (..)
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, Decl (..)
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, Lifetime (..)
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, NInputGateKW (..)
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, NOutputGateKW (..)
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, AST
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, PortBinding
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, ModportDecl
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, Case
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, GenCase
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, simplify
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, rangeSize
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, module Expr
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, module Op
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, module Type
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) where
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import Data.List (intercalate)
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import Data.Maybe (maybe, fromJust, isJust)
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import Text.Printf (printf)
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import Text.Read (readMaybe)
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import Text.Read (readMaybe)
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type Identifier = String
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import Language.SystemVerilog.AST.Expr as Expr
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import Language.SystemVerilog.AST.Op as Op
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import Language.SystemVerilog.AST.Type as Type
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import Language.SystemVerilog.AST.ShowHelp
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-- Note: Verilog allows modules to be declared with either a simple list of
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-- Note: Verilog allows modules to be declared with either a simple list of
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-- ports _identifiers_, or a list of port _declarations_. If only the
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-- ports _identifiers_, or a list of port _declarations_. If only the
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-- identifiers are used, they must be declared with a type and direction
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-- identifiers are used, they must be declared with a type and direction
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-- (potentially separately!) within the module itself.
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-- (potentially separately!) within the module itself.
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-- Note: This AST will allow for the representation of syntactically invalid
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-- things, like input regs. We might want to have a function for doing some
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-- basing invariant checks. I want to avoid making a full type-checker though,
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-- as we should only be given valid SystemVerilog input files.
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type AST = [Description]
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type AST = [Description]
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data PackageItem
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data PackageItem
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@ -119,146 +122,6 @@ instance Show Direction where
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show Inout = "inout"
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show Inout = "inout"
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show Local = ""
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show Local = ""
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data Signing
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= Unspecified
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| Signed
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| Unsigned
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deriving (Eq, Ord)
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instance Show Signing where
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show Unspecified = ""
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show Signed = "signed"
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show Unsigned = "unsigned"
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data NetType
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= TSupply0
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| TSupply1
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| TTri
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| TTriand
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| TTrior
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| TTrireg
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| TTri0
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| TTri1
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| TUwire
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| TWire
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| TWand
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| TWor
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deriving (Eq, Ord)
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data IntegerVectorType
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= TBit
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| TLogic
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| TReg
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deriving (Eq, Ord)
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data IntegerAtomType
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= TByte
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| TShortint
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| TInt
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| TLongint
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| TInteger
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| TTime
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deriving (Eq, Ord)
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data NonIntegerType
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= TShortreal
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| TReal
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| TRealtime
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deriving (Eq, Ord)
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instance Show NetType where
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show TSupply0 = "supply0"
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show TSupply1 = "supply1"
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show TTri = "tri"
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show TTriand = "triand"
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show TTrior = "trior"
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show TTrireg = "trireg"
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show TTri0 = "tri0"
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show TTri1 = "tri1"
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show TUwire = "uwire"
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show TWire = "wire"
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show TWand = "wand"
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show TWor = "wor"
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instance Show IntegerVectorType where
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show TBit = "bit"
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show TLogic = "logic"
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show TReg = "reg"
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instance Show IntegerAtomType where
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show TByte = "byte"
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show TShortint = "shortint"
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show TInt = "int"
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show TLongint = "longint"
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show TInteger = "integer"
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show TTime = "time"
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instance Show NonIntegerType where
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show TShortreal = "shortreal"
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show TReal = "real"
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show TRealtime = "realtime"
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data Packing
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= Unpacked
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| Packed Signing
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deriving (Eq, Ord)
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instance Show Packing where
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show (Unpacked) = ""
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show (Packed s) = "packed" ++ (showPadBefore s)
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type Item = (Identifier, Maybe Expr)
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type Field = (Type, Identifier)
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data Type
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= IntegerVector IntegerVectorType Signing [Range]
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| IntegerAtom IntegerAtomType Signing
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| NonInteger NonIntegerType
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| Net NetType [Range]
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| Implicit Signing [Range]
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| Alias Identifier [Range]
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| Enum (Maybe Type) [Item] [Range]
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| Struct Packing [Field] [Range]
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| InterfaceT Identifier (Maybe Identifier) [Range]
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deriving (Eq, Ord)
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instance Show Type where
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show (Alias xx rs) = printf "%s%s" xx (showRanges rs)
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show (Net kw rs) = printf "%s%s" (show kw) (showRanges rs)
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show (Implicit sg rs) = printf "%s%s" (show sg) (showRanges rs)
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show (IntegerVector kw sg rs) = printf "%s%s%s" (show kw) (showPadBefore sg) (showRanges rs)
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show (IntegerAtom kw sg ) = printf "%s%s" (show kw) (showPadBefore sg)
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show (NonInteger kw ) = printf "%s" (show kw)
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show (InterfaceT x my r) = x ++ yStr ++ (showRanges r)
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where yStr = maybe "" ("."++) my
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show (Enum mt vals r) = printf "enum %s{%s}%s" tStr (commas $ map showVal vals) (showRanges r)
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where
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tStr = maybe "" showPad mt
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showVal :: (Identifier, Maybe Expr) -> String
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showVal (x, e) = x ++ (showAssignment e)
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show (Struct p items r) = printf "struct %s{\n%s\n}%s" (showPad p) itemsStr (showRanges r)
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where
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itemsStr = indent $ unlines' $ map showItem items
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showItem (t, x) = printf "%s %s;" (show t) x
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instance Show ([Range] -> Type) where
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show tf = show (tf [])
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instance Eq ([Range] -> Type) where
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(==) tf1 tf2 = (tf1 []) == (tf2 [])
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instance Ord ([Range] -> Type) where
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compare tf1 tf2 = compare (tf1 []) (tf2 [])
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instance Show (Signing -> [Range] -> Type) where
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show tf = show (tf Unspecified)
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instance Eq (Signing -> [Range] -> Type) where
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(==) tf1 tf2 = (tf1 Unspecified) == (tf2 Unspecified)
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instance Ord (Signing -> [Range] -> Type) where
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compare tf1 tf2 = compare (tf1 Unspecified) (tf2 Unspecified)
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typeRanges :: Type -> ([Range] -> Type, [Range])
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typeRanges (Alias xx rs) = (Alias xx , rs)
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typeRanges (Net kw rs) = (Net kw , rs)
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typeRanges (Implicit sg rs) = (Implicit sg, rs)
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typeRanges (IntegerVector kw sg rs) = (IntegerVector kw sg, rs)
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typeRanges (IntegerAtom kw sg ) = (\[] -> IntegerAtom kw sg, [])
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typeRanges (NonInteger kw ) = (\[] -> NonInteger kw , [])
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typeRanges (Enum t v r) = (Enum t v, r)
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typeRanges (Struct p l r) = (Struct p l, r)
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typeRanges (InterfaceT x my r) = (InterfaceT x my, r)
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data Decl
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data Decl
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= Parameter Type Identifier Expr
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= Parameter Type Identifier Expr
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| Localparam Type Identifier Expr
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| Localparam Type Identifier Expr
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@ -357,176 +220,6 @@ instance Show NOutputGateKW where
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show GateBuf = "buf"
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show GateBuf = "buf"
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show GateNot = "not"
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show GateNot = "not"
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showAssignment :: Maybe Expr -> String
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showAssignment Nothing = ""
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showAssignment (Just val) = " = " ++ show val
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showRanges :: [Range] -> String
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showRanges [] = ""
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showRanges l = " " ++ (concat $ map rangeToString l)
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where rangeToString d = init $ showRange $ Just d
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showRange :: Maybe Range -> String
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showRange Nothing = ""
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showRange (Just (h, l)) = printf "[%s:%s] " (show h) (show l)
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showPad :: Show t => t -> String
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showPad x =
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if str == ""
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then ""
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else str ++ " "
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where str = show x
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showPadBefore :: Show t => t -> String
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showPadBefore x =
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if str == ""
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then ""
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else " " ++ str
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where str = show x
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indent :: String -> String
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indent a = '\t' : f a
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where
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f [] = []
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f (x : xs)
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| x == '\n' = "\n\t" ++ f xs
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| otherwise = x : f xs
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unlines' :: [String] -> String
|
|
||||||
unlines' = intercalate "\n"
|
|
||||||
|
|
||||||
data Expr
|
|
||||||
= String String
|
|
||||||
| Number String
|
|
||||||
| ConstBool Bool
|
|
||||||
| Ident Identifier
|
|
||||||
| Range Expr Range
|
|
||||||
| Bit Expr Expr
|
|
||||||
| Repeat Expr [Expr]
|
|
||||||
| Concat [Expr]
|
|
||||||
| Call Identifier [Maybe Expr]
|
|
||||||
| UniOp UniOp Expr
|
|
||||||
| BinOp BinOp Expr Expr
|
|
||||||
| Mux Expr Expr Expr
|
|
||||||
| Cast Type Expr
|
|
||||||
| Access Expr Identifier
|
|
||||||
| Pattern [(Maybe Identifier, Expr)]
|
|
||||||
deriving (Eq, Ord)
|
|
||||||
|
|
||||||
data UniOp
|
|
||||||
= Not
|
|
||||||
| BWNot
|
|
||||||
| UAdd
|
|
||||||
| USub
|
|
||||||
| RedAnd
|
|
||||||
| RedNand
|
|
||||||
| RedOr
|
|
||||||
| RedNor
|
|
||||||
| RedXor
|
|
||||||
| RedXnor
|
|
||||||
deriving (Eq, Ord)
|
|
||||||
|
|
||||||
instance Show UniOp where
|
|
||||||
show Not = "!"
|
|
||||||
show BWNot = "~"
|
|
||||||
show UAdd = "+"
|
|
||||||
show USub = "-"
|
|
||||||
show RedAnd = "&"
|
|
||||||
show RedNand = "~&"
|
|
||||||
show RedOr = "|"
|
|
||||||
show RedNor = "~|"
|
|
||||||
show RedXor = "^"
|
|
||||||
show RedXnor = "~^"
|
|
||||||
|
|
||||||
data BinOp
|
|
||||||
= And
|
|
||||||
| Or
|
|
||||||
| BWAnd
|
|
||||||
| BWXor
|
|
||||||
| BWOr
|
|
||||||
| Mul
|
|
||||||
| Div
|
|
||||||
| Mod
|
|
||||||
| Add
|
|
||||||
| Sub
|
|
||||||
| ShiftL
|
|
||||||
| ShiftR
|
|
||||||
| Eq
|
|
||||||
| Ne
|
|
||||||
| Lt
|
|
||||||
| Le
|
|
||||||
| Gt
|
|
||||||
| Ge
|
|
||||||
| Pow
|
|
||||||
| ShiftAL
|
|
||||||
| ShiftAR
|
|
||||||
| TEq
|
|
||||||
| TNe
|
|
||||||
| WEq
|
|
||||||
| WNe
|
|
||||||
deriving (Eq, Ord)
|
|
||||||
|
|
||||||
instance Show BinOp where
|
|
||||||
show a = case a of
|
|
||||||
And -> "&&"
|
|
||||||
Or -> "||"
|
|
||||||
BWAnd -> "&"
|
|
||||||
BWXor -> "^"
|
|
||||||
BWOr -> "|"
|
|
||||||
Mul -> "*"
|
|
||||||
Div -> "/"
|
|
||||||
Mod -> "%"
|
|
||||||
Add -> "+"
|
|
||||||
Sub -> "-"
|
|
||||||
ShiftL -> "<<"
|
|
||||||
ShiftR -> ">>"
|
|
||||||
Eq -> "=="
|
|
||||||
Ne -> "!="
|
|
||||||
Lt -> "<"
|
|
||||||
Le -> "<="
|
|
||||||
Gt -> ">"
|
|
||||||
Ge -> ">="
|
|
||||||
Pow -> "**"
|
|
||||||
ShiftAL -> "<<<"
|
|
||||||
ShiftAR -> ">>>"
|
|
||||||
TEq -> "==="
|
|
||||||
TNe -> "!=="
|
|
||||||
WEq -> "==?"
|
|
||||||
WNe -> "!=?"
|
|
||||||
|
|
||||||
instance Show Expr where
|
|
||||||
show x = case x of
|
|
||||||
String a -> printf "\"%s\"" a
|
|
||||||
Number a -> a
|
|
||||||
ConstBool a -> printf "1'b%s" (if a then "1" else "0")
|
|
||||||
Ident a -> a
|
|
||||||
Bit a b -> printf "%s[%s]" (show a) (show b)
|
|
||||||
Range a (b, c) -> printf "%s[%s:%s]" (show a) (show b) (show c)
|
|
||||||
Repeat a b -> printf "{%s {%s}}" (show a) (commas $ map show b)
|
|
||||||
Concat a -> printf "{%s}" (commas $ map show a)
|
|
||||||
Call a b -> printf "%s(%s)" a (commas $ map (maybe "" show) b)
|
|
||||||
UniOp a b -> printf "(%s %s)" (show a) (show b)
|
|
||||||
BinOp a b c -> printf "(%s %s %s)" (show b) (show a) (show c)
|
|
||||||
Mux a b c -> printf "(%s ? %s : %s)" (show a) (show b) (show c)
|
|
||||||
Cast a b -> printf "%s'(%s)" (show a) (show b)
|
|
||||||
Access e n -> printf "%s.%s" (show e) n
|
|
||||||
Pattern l -> printf "'{\n%s\n}" (showPatternItems l)
|
|
||||||
where
|
|
||||||
showPatternItems :: [(Maybe Identifier, Expr)] -> String
|
|
||||||
showPatternItems l = indent $ intercalate ",\n" (map showPatternItem l)
|
|
||||||
showPatternItem :: (Maybe Identifier, Expr) -> String
|
|
||||||
showPatternItem (Nothing, e) = show e
|
|
||||||
showPatternItem (Just n , e) = printf "%s: %s" n (show e)
|
|
||||||
|
|
||||||
data AsgnOp
|
|
||||||
= AsgnOpEq
|
|
||||||
| AsgnOp BinOp
|
|
||||||
deriving Eq
|
|
||||||
|
|
||||||
instance Show AsgnOp where
|
|
||||||
show AsgnOpEq = "="
|
|
||||||
show (AsgnOp op) = (show op) ++ "="
|
|
||||||
|
|
||||||
data LHS
|
data LHS
|
||||||
= LHSIdent Identifier
|
= LHSIdent Identifier
|
||||||
| LHSBit LHS Expr
|
| LHSBit LHS Expr
|
||||||
|
|
@ -570,9 +263,6 @@ data Stmt
|
||||||
| Null
|
| Null
|
||||||
deriving Eq
|
deriving Eq
|
||||||
|
|
||||||
commas :: [String] -> String
|
|
||||||
commas = intercalate ", "
|
|
||||||
|
|
||||||
instance Show Stmt where
|
instance Show Stmt where
|
||||||
show (Block name decls stmts) =
|
show (Block name decls stmts) =
|
||||||
printf "begin%s\n%s\n%s\nend" header (block decls) (block stmts)
|
printf "begin%s\n%s\n%s\nend" header (block decls) (block stmts)
|
||||||
|
|
@ -637,14 +327,6 @@ instance Show Sense where
|
||||||
show (SenseNegedge a ) = printf "negedge %s" (show a)
|
show (SenseNegedge a ) = printf "negedge %s" (show a)
|
||||||
show (SenseStar ) = "*"
|
show (SenseStar ) = "*"
|
||||||
|
|
||||||
type Range = (Expr, Expr)
|
|
||||||
|
|
||||||
indentedParenList :: [String] -> String
|
|
||||||
indentedParenList [] = "()"
|
|
||||||
indentedParenList [x] = "(" ++ x ++ ")"
|
|
||||||
indentedParenList l =
|
|
||||||
"(\n" ++ (indent $ intercalate ",\n" l) ++ "\n)"
|
|
||||||
|
|
||||||
type GenCase = ([Expr], GenItem)
|
type GenCase = ([Expr], GenItem)
|
||||||
|
|
||||||
data GenItem
|
data GenItem
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,71 @@
|
||||||
|
{- sv2v
|
||||||
|
- Author: Zachary Snow <zach@zachjs.com>
|
||||||
|
- Initial Verilog AST Author: Tom Hawkins <tomahawkins@gmail.com>
|
||||||
|
-
|
||||||
|
- SystemVerilog expressions
|
||||||
|
-}
|
||||||
|
|
||||||
|
module Language.SystemVerilog.AST.Expr
|
||||||
|
( Expr (..)
|
||||||
|
, Range
|
||||||
|
, showAssignment
|
||||||
|
, showRanges
|
||||||
|
) where
|
||||||
|
|
||||||
|
import Data.List (intercalate)
|
||||||
|
import Text.Printf (printf)
|
||||||
|
|
||||||
|
import Language.SystemVerilog.AST.Op
|
||||||
|
import Language.SystemVerilog.AST.ShowHelp
|
||||||
|
import {-# SOURCE #-} Language.SystemVerilog.AST.Type
|
||||||
|
|
||||||
|
type Range = (Expr, Expr)
|
||||||
|
|
||||||
|
data Expr
|
||||||
|
= String String
|
||||||
|
| Number String
|
||||||
|
| Ident Identifier
|
||||||
|
| Range Expr Range
|
||||||
|
| Bit Expr Expr
|
||||||
|
| Repeat Expr [Expr]
|
||||||
|
| Concat [Expr]
|
||||||
|
| Call Identifier [Maybe Expr]
|
||||||
|
| UniOp UniOp Expr
|
||||||
|
| BinOp BinOp Expr Expr
|
||||||
|
| Mux Expr Expr Expr
|
||||||
|
| Cast Type Expr
|
||||||
|
| Dot Expr Identifier
|
||||||
|
| Pattern [(Maybe Identifier, Expr)]
|
||||||
|
deriving (Eq, Ord)
|
||||||
|
|
||||||
|
instance Show Expr where
|
||||||
|
show (Number str ) = str
|
||||||
|
show (Ident str ) = str
|
||||||
|
show (String str ) = printf "\"%s\"" str
|
||||||
|
show (Bit e b ) = printf "%s[%s]" (show e) (show b)
|
||||||
|
show (Range e r ) = printf "%s%s" (show e) (showRange r)
|
||||||
|
show (Repeat e l ) = printf "{%s {%s}}" (show e) (commas $ map show l)
|
||||||
|
show (Concat l ) = printf "{%s}" (commas $ map show l)
|
||||||
|
show (UniOp a b ) = printf "(%s %s)" (show a) (show b)
|
||||||
|
show (BinOp a o b) = printf "(%s %s %s)" (show a) (show o) (show b)
|
||||||
|
show (Cast t e ) = printf "%s'(%s)" (show t) (show e)
|
||||||
|
show (Dot e n ) = printf "%s.%s" (show e) n
|
||||||
|
show (Mux c a b) = printf "(%s ? %s : %s)" (show c) (show a) (show b)
|
||||||
|
show (Call f l ) = printf "%s(%s)" f (commas $ map (maybe "" show) l)
|
||||||
|
show (Pattern l ) =
|
||||||
|
printf "'{\n%s\n}" (indent $ intercalate ",\n" $ map showPatternItem l)
|
||||||
|
where
|
||||||
|
showPatternItem :: (Maybe Identifier, Expr) -> String
|
||||||
|
showPatternItem (Nothing, e) = show e
|
||||||
|
showPatternItem (Just n , e) = printf "%s: %s" n (show e)
|
||||||
|
|
||||||
|
showAssignment :: Maybe Expr -> String
|
||||||
|
showAssignment Nothing = ""
|
||||||
|
showAssignment (Just val) = " = " ++ show val
|
||||||
|
|
||||||
|
showRanges :: [Range] -> String
|
||||||
|
showRanges [] = ""
|
||||||
|
showRanges l = " " ++ (concatMap showRange l)
|
||||||
|
|
||||||
|
showRange :: Range -> String
|
||||||
|
showRange (h, l) = printf "[%s:%s]" (show h) (show l)
|
||||||
|
|
@ -0,0 +1,101 @@
|
||||||
|
{- sv2v
|
||||||
|
- Author: Zachary Snow <zach@zachjs.com>
|
||||||
|
- Initial Verilog AST Author: Tom Hawkins <tomahawkins@gmail.com>
|
||||||
|
-
|
||||||
|
- SystemVerilog operators (unary, binary, and assignment)
|
||||||
|
-}
|
||||||
|
|
||||||
|
module Language.SystemVerilog.AST.Op
|
||||||
|
( UniOp (..)
|
||||||
|
, BinOp (..)
|
||||||
|
, AsgnOp (..)
|
||||||
|
) where
|
||||||
|
|
||||||
|
data UniOp
|
||||||
|
= LogNot
|
||||||
|
| BitNot
|
||||||
|
| UniAdd
|
||||||
|
| UniSub
|
||||||
|
| RedAnd
|
||||||
|
| RedNand
|
||||||
|
| RedOr
|
||||||
|
| RedNor
|
||||||
|
| RedXor
|
||||||
|
| RedXnor
|
||||||
|
deriving (Eq, Ord)
|
||||||
|
|
||||||
|
instance Show UniOp where
|
||||||
|
show LogNot = "!"
|
||||||
|
show BitNot = "~"
|
||||||
|
show UniAdd = "+"
|
||||||
|
show UniSub = "-"
|
||||||
|
show RedAnd = "&"
|
||||||
|
show RedNand = "~&"
|
||||||
|
show RedOr = "|"
|
||||||
|
show RedNor = "~|"
|
||||||
|
show RedXor = "^"
|
||||||
|
show RedXnor = "~^"
|
||||||
|
|
||||||
|
data BinOp
|
||||||
|
= LogAnd
|
||||||
|
| LogOr
|
||||||
|
| BitAnd
|
||||||
|
| BitXor
|
||||||
|
| BitOr
|
||||||
|
| Mul
|
||||||
|
| Div
|
||||||
|
| Mod
|
||||||
|
| Add
|
||||||
|
| Sub
|
||||||
|
| Pow
|
||||||
|
| ShiftL
|
||||||
|
| ShiftR
|
||||||
|
| ShiftAL
|
||||||
|
| ShiftAR
|
||||||
|
| Eq
|
||||||
|
| Ne
|
||||||
|
| TEq
|
||||||
|
| TNe
|
||||||
|
| WEq
|
||||||
|
| WNe
|
||||||
|
| Lt
|
||||||
|
| Le
|
||||||
|
| Gt
|
||||||
|
| Ge
|
||||||
|
deriving (Eq, Ord)
|
||||||
|
|
||||||
|
instance Show BinOp where
|
||||||
|
show LogAnd = "&&"
|
||||||
|
show LogOr = "||"
|
||||||
|
show BitAnd = "&"
|
||||||
|
show BitXor = "^"
|
||||||
|
show BitOr = "|"
|
||||||
|
show Mul = "*"
|
||||||
|
show Div = "/"
|
||||||
|
show Mod = "%"
|
||||||
|
show Add = "+"
|
||||||
|
show Sub = "-"
|
||||||
|
show Pow = "**"
|
||||||
|
show ShiftL = "<<"
|
||||||
|
show ShiftR = ">>"
|
||||||
|
show ShiftAL = "<<<"
|
||||||
|
show ShiftAR = ">>>"
|
||||||
|
show Eq = "=="
|
||||||
|
show Ne = "!="
|
||||||
|
show TEq = "==="
|
||||||
|
show TNe = "!=="
|
||||||
|
show WEq = "==?"
|
||||||
|
show WNe = "!=?"
|
||||||
|
show Lt = "<"
|
||||||
|
show Le = "<="
|
||||||
|
show Gt = ">"
|
||||||
|
show Ge = ">="
|
||||||
|
|
||||||
|
data AsgnOp
|
||||||
|
= AsgnOpEq
|
||||||
|
| AsgnOp BinOp
|
||||||
|
deriving (Eq, Ord)
|
||||||
|
|
||||||
|
instance Show AsgnOp where
|
||||||
|
show AsgnOpEq = "="
|
||||||
|
show (AsgnOp op) = (show op) ++ "="
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
{- sv2v
|
||||||
|
- Author: Zachary Snow <zach@zachjs.com>
|
||||||
|
- Initial Verilog AST Author: Tom Hawkins <tomahawkins@gmail.com>
|
||||||
|
-
|
||||||
|
- Helpers for printing AST items
|
||||||
|
-}
|
||||||
|
|
||||||
|
module Language.SystemVerilog.AST.ShowHelp
|
||||||
|
( showPad
|
||||||
|
, showPadBefore
|
||||||
|
, indent
|
||||||
|
, unlines'
|
||||||
|
, commas
|
||||||
|
, indentedParenList
|
||||||
|
) where
|
||||||
|
|
||||||
|
import Data.List (intercalate)
|
||||||
|
|
||||||
|
showPad :: Show t => t -> String
|
||||||
|
showPad x =
|
||||||
|
if str == ""
|
||||||
|
then ""
|
||||||
|
else str ++ " "
|
||||||
|
where str = show x
|
||||||
|
|
||||||
|
showPadBefore :: Show t => t -> String
|
||||||
|
showPadBefore x =
|
||||||
|
if str == ""
|
||||||
|
then ""
|
||||||
|
else " " ++ str
|
||||||
|
where str = show x
|
||||||
|
|
||||||
|
indent :: String -> String
|
||||||
|
indent a = '\t' : f a
|
||||||
|
where
|
||||||
|
f [] = []
|
||||||
|
f ('\n' : xs) = "\n\t" ++ f xs
|
||||||
|
f (x : xs) = x : f xs
|
||||||
|
|
||||||
|
unlines' :: [String] -> String
|
||||||
|
unlines' = intercalate "\n"
|
||||||
|
|
||||||
|
commas :: [String] -> String
|
||||||
|
commas = intercalate ", "
|
||||||
|
|
||||||
|
indentedParenList :: [String] -> String
|
||||||
|
indentedParenList [] = "()"
|
||||||
|
indentedParenList [x] = "(" ++ x ++ ")"
|
||||||
|
indentedParenList l = "(\n" ++ (indent $ intercalate ",\n" l) ++ "\n)"
|
||||||
|
|
||||||
|
|
@ -0,0 +1,167 @@
|
||||||
|
{-# LANGUAGE FlexibleInstances #-}
|
||||||
|
{- sv2v
|
||||||
|
- Author: Zachary Snow <zach@zachjs.com>
|
||||||
|
- Initial Verilog AST Author: Tom Hawkins <tomahawkins@gmail.com>
|
||||||
|
-
|
||||||
|
- SystemVerilog types
|
||||||
|
-}
|
||||||
|
|
||||||
|
module Language.SystemVerilog.AST.Type
|
||||||
|
( Identifier
|
||||||
|
, Type (..)
|
||||||
|
, Signing (..)
|
||||||
|
, Packing (..)
|
||||||
|
, NetType (..)
|
||||||
|
, IntegerVectorType (..)
|
||||||
|
, IntegerAtomType (..)
|
||||||
|
, NonIntegerType (..)
|
||||||
|
, typeRanges
|
||||||
|
) where
|
||||||
|
|
||||||
|
import Text.Printf (printf)
|
||||||
|
|
||||||
|
import Language.SystemVerilog.AST.Expr
|
||||||
|
import Language.SystemVerilog.AST.ShowHelp
|
||||||
|
|
||||||
|
type Identifier = String
|
||||||
|
|
||||||
|
type Item = (Identifier, Maybe Expr)
|
||||||
|
type Field = (Type, Identifier)
|
||||||
|
|
||||||
|
data Type
|
||||||
|
= IntegerVector IntegerVectorType Signing [Range]
|
||||||
|
| IntegerAtom IntegerAtomType Signing
|
||||||
|
| NonInteger NonIntegerType
|
||||||
|
| Net NetType [Range]
|
||||||
|
| Implicit Signing [Range]
|
||||||
|
| Alias Identifier [Range]
|
||||||
|
| Enum (Maybe Type) [Item] [Range]
|
||||||
|
| Struct Packing [Field] [Range]
|
||||||
|
| InterfaceT Identifier (Maybe Identifier) [Range]
|
||||||
|
deriving (Eq, Ord)
|
||||||
|
|
||||||
|
instance Show Type where
|
||||||
|
show (Alias xx rs) = printf "%s%s" xx (showRanges rs)
|
||||||
|
show (Net kw rs) = printf "%s%s" (show kw) (showRanges rs)
|
||||||
|
show (Implicit sg rs) = printf "%s%s" (show sg) (showRanges rs)
|
||||||
|
show (IntegerVector kw sg rs) = printf "%s%s%s" (show kw) (showPadBefore sg) (showRanges rs)
|
||||||
|
show (IntegerAtom kw sg ) = printf "%s%s" (show kw) (showPadBefore sg)
|
||||||
|
show (NonInteger kw ) = printf "%s" (show kw)
|
||||||
|
show (InterfaceT x my r) = x ++ yStr ++ (showRanges r)
|
||||||
|
where yStr = maybe "" ("."++) my
|
||||||
|
show (Enum mt vals r) = printf "enum %s{%s}%s" tStr (commas $ map showVal vals) (showRanges r)
|
||||||
|
where
|
||||||
|
tStr = maybe "" showPad mt
|
||||||
|
showVal :: (Identifier, Maybe Expr) -> String
|
||||||
|
showVal (x, e) = x ++ (showAssignment e)
|
||||||
|
show (Struct p items r) = printf "struct %s{\n%s\n}%s" (showPad p) itemsStr (showRanges r)
|
||||||
|
where
|
||||||
|
itemsStr = indent $ unlines' $ map showItem items
|
||||||
|
showItem (t, x) = printf "%s %s;" (show t) x
|
||||||
|
|
||||||
|
instance Show ([Range] -> Type) where
|
||||||
|
show tf = show (tf [])
|
||||||
|
instance Eq ([Range] -> Type) where
|
||||||
|
(==) tf1 tf2 = (tf1 []) == (tf2 [])
|
||||||
|
instance Ord ([Range] -> Type) where
|
||||||
|
compare tf1 tf2 = compare (tf1 []) (tf2 [])
|
||||||
|
|
||||||
|
instance Show (Signing -> [Range] -> Type) where
|
||||||
|
show tf = show (tf Unspecified)
|
||||||
|
instance Eq (Signing -> [Range] -> Type) where
|
||||||
|
(==) tf1 tf2 = (tf1 Unspecified) == (tf2 Unspecified)
|
||||||
|
instance Ord (Signing -> [Range] -> Type) where
|
||||||
|
compare tf1 tf2 = compare (tf1 Unspecified) (tf2 Unspecified)
|
||||||
|
|
||||||
|
typeRanges :: Type -> ([Range] -> Type, [Range])
|
||||||
|
typeRanges (Alias xx rs) = (Alias xx , rs)
|
||||||
|
typeRanges (Net kw rs) = (Net kw , rs)
|
||||||
|
typeRanges (Implicit sg rs) = (Implicit sg, rs)
|
||||||
|
typeRanges (IntegerVector kw sg rs) = (IntegerVector kw sg, rs)
|
||||||
|
typeRanges (IntegerAtom kw sg ) = (\[] -> IntegerAtom kw sg, [])
|
||||||
|
typeRanges (NonInteger kw ) = (\[] -> NonInteger kw , [])
|
||||||
|
typeRanges (Enum t v r) = (Enum t v, r)
|
||||||
|
typeRanges (Struct p l r) = (Struct p l, r)
|
||||||
|
typeRanges (InterfaceT x my r) = (InterfaceT x my, r)
|
||||||
|
|
||||||
|
data Signing
|
||||||
|
= Unspecified
|
||||||
|
| Signed
|
||||||
|
| Unsigned
|
||||||
|
deriving (Eq, Ord)
|
||||||
|
|
||||||
|
instance Show Signing where
|
||||||
|
show Unspecified = ""
|
||||||
|
show Signed = "signed"
|
||||||
|
show Unsigned = "unsigned"
|
||||||
|
|
||||||
|
data NetType
|
||||||
|
= TSupply0
|
||||||
|
| TSupply1
|
||||||
|
| TTri
|
||||||
|
| TTriand
|
||||||
|
| TTrior
|
||||||
|
| TTrireg
|
||||||
|
| TTri0
|
||||||
|
| TTri1
|
||||||
|
| TUwire
|
||||||
|
| TWire
|
||||||
|
| TWand
|
||||||
|
| TWor
|
||||||
|
deriving (Eq, Ord)
|
||||||
|
data IntegerVectorType
|
||||||
|
= TBit
|
||||||
|
| TLogic
|
||||||
|
| TReg
|
||||||
|
deriving (Eq, Ord)
|
||||||
|
data IntegerAtomType
|
||||||
|
= TByte
|
||||||
|
| TShortint
|
||||||
|
| TInt
|
||||||
|
| TLongint
|
||||||
|
| TInteger
|
||||||
|
| TTime
|
||||||
|
deriving (Eq, Ord)
|
||||||
|
data NonIntegerType
|
||||||
|
= TShortreal
|
||||||
|
| TReal
|
||||||
|
| TRealtime
|
||||||
|
deriving (Eq, Ord)
|
||||||
|
|
||||||
|
instance Show NetType where
|
||||||
|
show TSupply0 = "supply0"
|
||||||
|
show TSupply1 = "supply1"
|
||||||
|
show TTri = "tri"
|
||||||
|
show TTriand = "triand"
|
||||||
|
show TTrior = "trior"
|
||||||
|
show TTrireg = "trireg"
|
||||||
|
show TTri0 = "tri0"
|
||||||
|
show TTri1 = "tri1"
|
||||||
|
show TUwire = "uwire"
|
||||||
|
show TWire = "wire"
|
||||||
|
show TWand = "wand"
|
||||||
|
show TWor = "wor"
|
||||||
|
instance Show IntegerVectorType where
|
||||||
|
show TBit = "bit"
|
||||||
|
show TLogic = "logic"
|
||||||
|
show TReg = "reg"
|
||||||
|
instance Show IntegerAtomType where
|
||||||
|
show TByte = "byte"
|
||||||
|
show TShortint = "shortint"
|
||||||
|
show TInt = "int"
|
||||||
|
show TLongint = "longint"
|
||||||
|
show TInteger = "integer"
|
||||||
|
show TTime = "time"
|
||||||
|
instance Show NonIntegerType where
|
||||||
|
show TShortreal = "shortreal"
|
||||||
|
show TReal = "real"
|
||||||
|
show TRealtime = "realtime"
|
||||||
|
|
||||||
|
data Packing
|
||||||
|
= Unpacked
|
||||||
|
| Packed Signing
|
||||||
|
deriving (Eq, Ord)
|
||||||
|
|
||||||
|
instance Show Packing where
|
||||||
|
show (Unpacked) = ""
|
||||||
|
show (Packed s) = "packed" ++ (showPadBefore s)
|
||||||
|
|
@ -0,0 +1,11 @@
|
||||||
|
module Language.SystemVerilog.AST.Type
|
||||||
|
( Identifier
|
||||||
|
, Type
|
||||||
|
) where
|
||||||
|
|
||||||
|
type Identifier = String
|
||||||
|
|
||||||
|
data Type
|
||||||
|
instance Eq Type
|
||||||
|
instance Ord Type
|
||||||
|
instance Show Type
|
||||||
|
|
@ -207,7 +207,7 @@ directive { Token Spe_Directive _ _ }
|
||||||
%left "+" "-"
|
%left "+" "-"
|
||||||
%left "*" "/" "%"
|
%left "*" "/" "%"
|
||||||
%left "**"
|
%left "**"
|
||||||
%right UPlus UMinus "!" "~" RedOps "++" "--"
|
%right REDUCE_OP "!" "~" "++" "--"
|
||||||
%left "(" ")" "[" "]" "."
|
%left "(" ")" "[" "]" "."
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -618,60 +618,62 @@ CallArgsFollow :: { [Maybe Expr] }
|
||||||
| "," opt(Expr) CallArgsFollow { $2 : $3 }
|
| "," opt(Expr) CallArgsFollow { $2 : $3 }
|
||||||
|
|
||||||
Exprs :: { [Expr] }
|
Exprs :: { [Expr] }
|
||||||
: Expr { [$1] }
|
: Expr { [$1] }
|
||||||
| Exprs "," Expr { $1 ++ [$3] }
|
| Exprs "," Expr { $1 ++ [$3] }
|
||||||
|
|
||||||
Expr :: { Expr }
|
Expr :: { Expr }
|
||||||
: "(" Expr ")" { $2 }
|
: "(" Expr ")" { $2 }
|
||||||
| String { String $1 }
|
| String { String $1 }
|
||||||
| Number { Number $1 }
|
| Number { Number $1 }
|
||||||
| Identifier "(" CallArgs ")" { Call $1 $3 }
|
| Identifier "(" CallArgs ")" { Call $1 $3 }
|
||||||
| Identifier { Ident $1 }
|
| Identifier { Ident $1 }
|
||||||
| Expr Range { Range $1 $2 }
|
| Expr Range { Range $1 $2 }
|
||||||
| Expr "[" Expr "]" { Bit $1 $3 }
|
| Expr "[" Expr "]" { Bit $1 $3 }
|
||||||
| "{" Expr "{" Exprs "}" "}" { Repeat $2 $4 }
|
| "{" Expr "{" Exprs "}" "}" { Repeat $2 $4 }
|
||||||
| "{" Exprs "}" { Concat $2 }
|
| "{" Exprs "}" { Concat $2 }
|
||||||
| Expr "?" Expr ":" Expr { Mux $1 $3 $5 }
|
| Expr "?" Expr ":" Expr { Mux $1 $3 $5 }
|
||||||
| Expr "||" Expr { BinOp Or $1 $3 }
|
| CastingType "'" "(" Expr ")" { Cast ($1 ) $4 }
|
||||||
| Expr "&&" Expr { BinOp And $1 $3 }
|
| Identifier "'" "(" Expr ")" { Cast (Alias $1 []) $4 }
|
||||||
| Expr "|" Expr { BinOp BWOr $1 $3 }
|
| Expr "." Identifier { Dot $1 $3 }
|
||||||
| Expr "^" Expr { BinOp BWXor $1 $3 }
|
| "'" "{" PatternItems "}" { Pattern $3 }
|
||||||
| Expr "&" Expr { BinOp BWAnd $1 $3 }
|
-- binary expressions
|
||||||
| Expr "==" Expr { BinOp Eq $1 $3 }
|
| Expr "||" Expr { BinOp LogOr $1 $3 }
|
||||||
| Expr "!=" Expr { BinOp Ne $1 $3 }
|
| Expr "&&" Expr { BinOp LogAnd $1 $3 }
|
||||||
| Expr "<" Expr { BinOp Lt $1 $3 }
|
| Expr "|" Expr { BinOp BitOr $1 $3 }
|
||||||
| Expr "<=" Expr { BinOp Le $1 $3 }
|
| Expr "^" Expr { BinOp BitXor $1 $3 }
|
||||||
| Expr ">" Expr { BinOp Gt $1 $3 }
|
| Expr "&" Expr { BinOp BitAnd $1 $3 }
|
||||||
| Expr ">=" Expr { BinOp Ge $1 $3 }
|
| Expr "+" Expr { BinOp Add $1 $3 }
|
||||||
| Expr "<<" Expr { BinOp ShiftL $1 $3 }
|
| Expr "-" Expr { BinOp Sub $1 $3 }
|
||||||
| Expr ">>" Expr { BinOp ShiftR $1 $3 }
|
| Expr "*" Expr { BinOp Mul $1 $3 }
|
||||||
| Expr "+" Expr { BinOp Add $1 $3 }
|
| Expr "/" Expr { BinOp Div $1 $3 }
|
||||||
| Expr "-" Expr { BinOp Sub $1 $3 }
|
| Expr "%" Expr { BinOp Mod $1 $3 }
|
||||||
| Expr "*" Expr { BinOp Mul $1 $3 }
|
| Expr "**" Expr { BinOp Pow $1 $3 }
|
||||||
| Expr "/" Expr { BinOp Div $1 $3 }
|
| Expr "==" Expr { BinOp Eq $1 $3 }
|
||||||
| Expr "%" Expr { BinOp Mod $1 $3 }
|
| Expr "!=" Expr { BinOp Ne $1 $3 }
|
||||||
| Expr "**" Expr { BinOp Pow $1 $3 }
|
| Expr "<" Expr { BinOp Lt $1 $3 }
|
||||||
| Expr "<<<" Expr { BinOp ShiftAL $1 $3 }
|
| Expr "<=" Expr { BinOp Le $1 $3 }
|
||||||
| Expr ">>>" Expr { BinOp ShiftAR $1 $3 }
|
| Expr ">" Expr { BinOp Gt $1 $3 }
|
||||||
| Expr "===" Expr { BinOp TEq $1 $3 }
|
| Expr ">=" Expr { BinOp Ge $1 $3 }
|
||||||
| Expr "!==" Expr { BinOp TNe $1 $3 }
|
| Expr "===" Expr { BinOp TEq $1 $3 }
|
||||||
| Expr "==?" Expr { BinOp WEq $1 $3 }
|
| Expr "!==" Expr { BinOp TNe $1 $3 }
|
||||||
| Expr "!=?" Expr { BinOp WNe $1 $3 }
|
| Expr "==?" Expr { BinOp WEq $1 $3 }
|
||||||
| "!" Expr { UniOp Not $2 }
|
| Expr "!=?" Expr { BinOp WNe $1 $3 }
|
||||||
| "~" Expr { UniOp BWNot $2 }
|
| Expr "<<" Expr { BinOp ShiftL $1 $3 }
|
||||||
| "+" Expr %prec UPlus { UniOp UAdd $2 }
|
| Expr ">>" Expr { BinOp ShiftR $1 $3 }
|
||||||
| "-" Expr %prec UMinus { UniOp USub $2 }
|
| Expr "<<<" Expr { BinOp ShiftAL $1 $3 }
|
||||||
| "&" Expr %prec RedOps { UniOp RedAnd $2 }
|
| Expr ">>>" Expr { BinOp ShiftAR $1 $3 }
|
||||||
| "~&" Expr %prec RedOps { UniOp RedNand $2 }
|
-- unary expressions
|
||||||
| "|" Expr %prec RedOps { UniOp RedOr $2 }
|
| "!" Expr { UniOp LogNot $2 }
|
||||||
| "~|" Expr %prec RedOps { UniOp RedNor $2 }
|
| "~" Expr { UniOp BitNot $2 }
|
||||||
| "^" Expr %prec RedOps { UniOp RedXor $2 }
|
| "+" Expr %prec REDUCE_OP { UniOp UniAdd $2 }
|
||||||
| "~^" Expr %prec RedOps { UniOp RedXnor $2 }
|
| "-" Expr %prec REDUCE_OP { UniOp UniSub $2 }
|
||||||
| "^~" Expr %prec RedOps { UniOp RedXnor $2 }
|
| "&" Expr %prec REDUCE_OP { UniOp RedAnd $2 }
|
||||||
| CastingType "'" "(" Expr ")" { Cast ($1 ) $4 }
|
| "~&" Expr %prec REDUCE_OP { UniOp RedNand $2 }
|
||||||
| Identifier "'" "(" Expr ")" { Cast (Alias $1 []) $4 }
|
| "|" Expr %prec REDUCE_OP { UniOp RedOr $2 }
|
||||||
| Expr "." Identifier { Access $1 $3 }
|
| "~|" Expr %prec REDUCE_OP { UniOp RedNor $2 }
|
||||||
| "'" "{" PatternItems "}" { Pattern $3 }
|
| "^" Expr %prec REDUCE_OP { UniOp RedXor $2 }
|
||||||
|
| "~^" Expr %prec REDUCE_OP { UniOp RedXnor $2 }
|
||||||
|
| "^~" Expr %prec REDUCE_OP { UniOp RedXnor $2 }
|
||||||
|
|
||||||
PatternItems :: { [(Maybe Identifier, Expr)] }
|
PatternItems :: { [(Maybe Identifier, Expr)] }
|
||||||
: PatternNamedItems { map (\(x,e) -> (Just x, e)) $1 }
|
: PatternNamedItems { map (\(x,e) -> (Just x, e)) $1 }
|
||||||
|
|
@ -726,9 +728,9 @@ AsgnOp :: { AsgnOp }
|
||||||
| "*=" { AsgnOp Mul }
|
| "*=" { AsgnOp Mul }
|
||||||
| "/=" { AsgnOp Div }
|
| "/=" { AsgnOp Div }
|
||||||
| "%=" { AsgnOp Mod }
|
| "%=" { AsgnOp Mod }
|
||||||
| "&=" { AsgnOp BWAnd }
|
| "&=" { AsgnOp BitAnd }
|
||||||
| "|=" { AsgnOp BWOr }
|
| "|=" { AsgnOp BitOr }
|
||||||
| "^=" { AsgnOp BWXor }
|
| "^=" { AsgnOp BitXor }
|
||||||
| "<<=" { AsgnOp ShiftL }
|
| "<<=" { AsgnOp ShiftL }
|
||||||
| ">>=" { AsgnOp ShiftR }
|
| ">>=" { AsgnOp ShiftR }
|
||||||
| "<<<=" { AsgnOp ShiftAL }
|
| "<<<=" { AsgnOp ShiftAL }
|
||||||
|
|
@ -771,11 +773,11 @@ combineTags Nothing other = other
|
||||||
combineTags other _ = other
|
combineTags other _ = other
|
||||||
|
|
||||||
exprToLHS :: Expr -> LHS
|
exprToLHS :: Expr -> LHS
|
||||||
exprToLHS (Ident x) = LHSIdent x
|
exprToLHS (Ident x) = LHSIdent x
|
||||||
exprToLHS (Bit e b) = LHSBit (exprToLHS e) b
|
exprToLHS (Bit e b) = LHSBit (exprToLHS e) b
|
||||||
exprToLHS (Range e r) = LHSRange (exprToLHS e) r
|
exprToLHS (Range e r) = LHSRange (exprToLHS e) r
|
||||||
exprToLHS (Access e x) = LHSDot (exprToLHS e) x
|
exprToLHS (Dot e x) = LHSDot (exprToLHS e) x
|
||||||
exprToLHS (Concat es ) = LHSConcat (map exprToLHS es)
|
exprToLHS (Concat es) = LHSConcat (map exprToLHS es)
|
||||||
exprToLHS other =
|
exprToLHS other =
|
||||||
error $ "Parse error: cannot convert expression to LHS: " ++ show other
|
error $ "Parse error: cannot convert expression to LHS: " ++ show other
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -33,6 +33,10 @@ executable sv2v
|
||||||
-- SystemVerilog modules
|
-- SystemVerilog modules
|
||||||
Language.SystemVerilog
|
Language.SystemVerilog
|
||||||
Language.SystemVerilog.AST
|
Language.SystemVerilog.AST
|
||||||
|
Language.SystemVerilog.AST.Expr
|
||||||
|
Language.SystemVerilog.AST.Op
|
||||||
|
Language.SystemVerilog.AST.ShowHelp
|
||||||
|
Language.SystemVerilog.AST.Type
|
||||||
Language.SystemVerilog.Parser
|
Language.SystemVerilog.Parser
|
||||||
Language.SystemVerilog.Parser.Lex
|
Language.SystemVerilog.Parser.Lex
|
||||||
Language.SystemVerilog.Parser.Parse
|
Language.SystemVerilog.Parser.Parse
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue