mirror of https://github.com/zachjs/sv2v.git
75 lines
1.8 KiB
Plaintext
75 lines
1.8 KiB
Plaintext
name: sv2v
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version: 0.0.1
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synopsis: SystemVerilog to Verilog conversion
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description:
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A tool for coverting SystemVerilog to Verilog. Originally forked from the
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Verilog parser found at https://github.com/tomahawkins/verilog
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category: Language, Hardware, Embedded, Development
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author: Zachary Snow <zach@zachjs.com>, Tom Hawkins <tomahawkins@gmail.com>
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maintainer: Zachary Snow <zach@zachjs.com>
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license: BSD3
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license-file: LICENSE
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homepage: https://github.com/zachjs/sv2v
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build-type: Simple
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cabal-version: >= 1.12
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executable sv2v
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default-language: Haskell2010
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main-is: sv2v.hs
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hs-source-dirs: src
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build-tools:
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alex >= 3 && < 4,
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happy >= 1 && < 2
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build-depends:
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array,
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base,
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cmdargs,
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containers,
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filepath,
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mtl
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other-modules:
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-- SystemVerilog modules
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Language.SystemVerilog
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Language.SystemVerilog.AST
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Language.SystemVerilog.AST.Expr
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Language.SystemVerilog.AST.Op
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Language.SystemVerilog.AST.ShowHelp
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Language.SystemVerilog.AST.Type
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Language.SystemVerilog.Parser
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Language.SystemVerilog.Parser.Lex
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Language.SystemVerilog.Parser.Parse
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Language.SystemVerilog.Parser.ParseDecl
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Language.SystemVerilog.Parser.Preprocess
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Language.SystemVerilog.Parser.Tokens
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-- Conversion modules
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Convert
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Convert.AlwaysKW
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Convert.AsgnOp
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Convert.Enum
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Convert.FuncRet
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Convert.Interface
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Convert.Logic
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Convert.PackedArray
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Convert.Return
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Convert.StarPort
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Convert.Struct
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Convert.Typedef
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Convert.Traverse
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Convert.UnbasedUnsized
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Convert.Unique
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-- sv2v CLI modules
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Job
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ghc-options:
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-O3
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-threaded
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-rtsopts
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-with-rtsopts=-N
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-funbox-strict-fields
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-Wall
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source-repository head
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type: git
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location: git://github.com/zachjs/sv2v.git
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