mirror of https://github.com/zachjs/sv2v.git
fix typename decl asgn lookahead (resolves #49)
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@ -358,15 +358,25 @@ takeLifetime (DTLifetime l : rest) = (Just l, rest)
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takeLifetime rest = (Nothing, rest)
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takeLifetime rest = (Nothing, rest)
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takeType :: [DeclToken] -> ([Range] -> Type, [DeclToken])
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takeType :: [DeclToken] -> ([Range] -> Type, [DeclToken])
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takeType (DTIdent a : DTDot b : rest) = (InterfaceT a (Just b), rest)
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takeType (DTIdent a : DTDot b : rest) = (InterfaceT a (Just b), rest)
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takeType (DTType tf : DTSigning sg : rest) = (tf sg , rest)
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takeType (DTType tf : DTSigning sg : rest) = (tf sg , rest)
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takeType (DTType tf : rest) = (tf Unspecified, rest)
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takeType (DTType tf : rest) = (tf Unspecified , rest)
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takeType (DTSigning sg : rest) = (Implicit sg , rest)
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takeType (DTSigning sg : rest) = (Implicit sg , rest)
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takeType (DTIdent tn : DTComma : rest) = (Implicit Unspecified, DTIdent tn : DTComma : rest)
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takeType (DTPSIdent ps tn : rest) = (Alias (Just ps) tn , rest)
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takeType (DTIdent tn : [ ]) = (Implicit Unspecified, DTIdent tn : [ ])
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takeType (DTIdent tn : rest) =
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takeType (DTIdent tn : rest) = (Alias (Nothing) tn , rest)
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if couldBeTypename
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takeType (DTPSIdent ps tn : rest) = (Alias (Just ps) tn , rest)
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then (Alias (Nothing) tn , rest)
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takeType rest = (Implicit Unspecified, rest)
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else (Implicit Unspecified, DTIdent tn : rest)
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where
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couldBeTypename =
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case (findIndex isIdent rest, elemIndex DTComma rest) of
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-- no identifiers left => no decl asgns
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(Nothing, _) -> False
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-- an identifier is left, and no more commas
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(_, Nothing) -> True
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-- if comma is first, then this ident is a declaration
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(Just a, Just b) -> a < b
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takeType rest = (Implicit Unspecified, rest)
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takeRanges :: [DeclToken] -> ([Range], [DeclToken])
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takeRanges :: [DeclToken] -> ([Range], [DeclToken])
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takeRanges [] = ([], [])
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takeRanges [] = ([], [])
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@ -0,0 +1,7 @@
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typedef wire b_t;
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module top(
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input a [1:0],
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input b_t b
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);
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initial $display("%d %d %1d %1d", a, b, $bits(a), $bits(b));
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endmodule
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@ -0,0 +1,6 @@
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module top(
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input [1:0] a,
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input wire b
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);
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initial $display("%d %d %1d %1d", a, b, $bits(a), $bits(b));
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endmodule
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