diff --git a/src/Convert/Traverse.hs b/src/Convert/Traverse.hs
index 1ffc802..b18156a 100644
--- a/src/Convert/Traverse.hs
+++ b/src/Convert/Traverse.hs
@@ -201,6 +201,7 @@ traverseSinglyNestedStmtsM :: Monad m => MapperM m Stmt -> MapperM m Stmt
 traverseSinglyNestedStmtsM fullMapper = cs
     where
         cs (StmtAttr a stmt) = fullMapper stmt >>= return . StmtAttr a
+        cs (Block Nothing [] []) = return Null
         cs (Block name decls stmts) =
             mapM fullMapper stmts >>= return . Block name decls
         cs (Case u kw expr cases def) = do
diff --git a/src/Language/SystemVerilog/AST/Decl.hs b/src/Language/SystemVerilog/AST/Decl.hs
index f82a88e..d82a934 100644
--- a/src/Language/SystemVerilog/AST/Decl.hs
+++ b/src/Language/SystemVerilog/AST/Decl.hs
@@ -26,7 +26,7 @@ instance Show Decl where
     showList l _ = unlines' $ map show l
     show (Parameter  t x e) = printf  "parameter %s%s = %s;" (showPad t) x (show e)
     show (Localparam t x e) = printf "localparam %s%s = %s;" (showPad t) x (show e)
-    show (Variable d t x a me) = printf "%s%s %s%s%s;" (showPad d) (show t) x (showRanges a) (showAssignment me)
+    show (Variable d t x a me) = printf "%s%s%s%s%s;" (showPad d) (showPad t) x (showRanges a) (showAssignment me)
 
 data Direction
     = Input