apply reordering in generate blocks

src/Convert/AsgnOp.hs

@@ -14,8 +14,8 @@ import Language.SystemVerilog.AST
 convert :: [AST] -> [AST]
 convert =
     map $ traverseDescriptions $ traverseModuleItems $
-    ( traverseStmts    convertStmt
-    . traverseGenItems convertGenItem
+    ( traverseStmts convertStmt
+    . traverseGenItems (traverseNestedGenItems convertGenItem)
     )
 
 convertGenItem :: GenItem -> GenItem

src/Convert/Package.hs

@@ -407,13 +407,27 @@ convertDescription _ other = other
 -- attempt to fix simple declaration order issues
 reorderItems :: [ModuleItem] -> [ModuleItem]
 reorderItems items =
-    addItems localPIs Set.empty (map addUsedPIs items)
+    addItems localPIs Set.empty $ map addUsedPIs $
+        map (traverseGenItems $ traverseNestedGenItems reorderGenItem) items
     where
         localPIs = Map.fromList $ concat $ mapMaybe toPIElem items
         toPIElem :: ModuleItem -> Maybe [(Identifier, PackageItem)]
         toPIElem (MIPackageItem item) = Just $ map (, item) (piNames item)
         toPIElem _ = Nothing
 
+-- attempt to declaration order issues within generate blocks
+reorderGenItem :: GenItem -> GenItem
+reorderGenItem (GenBlock name genItems) =
+    GenBlock name $ map unwrap $ reorderItems $ map wrap genItems
+    where
+        wrap :: GenItem -> ModuleItem
+        wrap (GenModuleItem item) = item
+        wrap item = Generate [item]
+        unwrap :: ModuleItem -> GenItem
+        unwrap (Generate [item]) = item
+        unwrap item = GenModuleItem item
+reorderGenItem item = item
+
 -- iteratively inserts missing package items exactly where they are needed
 addItems :: PIs -> Idents -> [(ModuleItem, Idents)] -> [ModuleItem]
 addItems pis existingPIs ((item, usedPIs) : items) =
@@ -523,7 +537,6 @@ traverseStmtIdentsM identMapper = fullMapper
         fullMapper = stmtMapper
             >=> traverseStmtExprsM (traverseExprIdentsM identMapper)
             >=> traverseStmtLHSsM  (traverseLHSIdentsM  identMapper)
-            >=> traverseSinglyNestedStmtsM fullMapper
         stmtMapper (Subroutine (Ident x) args) =
             identMapper x >>= \x' -> return $ Subroutine (Ident x') args
         stmtMapper other = return other

src/Convert/Traverse.hs

@@ -978,9 +978,8 @@ collectTypesM = collectTypesM' IncludeParamTypes
 traverseGenItemsM :: Monad m => MapperM m GenItem -> MapperM m ModuleItem
 traverseGenItemsM mapper = moduleItemMapper
     where
-        fullMapper = traverseNestedGenItemsM mapper
         moduleItemMapper (Generate genItems) =
-            mapM fullMapper genItems >>= return . Generate
+            mapM mapper genItems >>= return . Generate
         moduleItemMapper other = return other
 
 traverseGenItems :: Mapper GenItem -> Mapper ModuleItem

test/basic/reorder.sv

@@ -2,4 +2,15 @@ module top;
     assign arr[0][0] = 1;
     logic [1:0][2:0] arr;
     initial $display("%b", arr);
+    parameter YES = 1;
+    if (YES) begin : blk
+        assign brr[0][0] = 1;
+        logic [2:0][3:0] brr;
+        initial $display("%b", brr);
+        if (YES) begin : blk2
+            assign crr[0][0] = 1;
+            logic [3:0][4:0] crr;
+            initial $display("%b", crr);
+        end
+    end
 endmodule

test/basic/reorder.v

@@ -2,4 +2,17 @@ module top;
     wire [5:0] arr;
     assign arr[0] = 1;
     initial $display("%b", arr);
+    parameter YES = 1;
+    generate
+        if (YES) begin : blk
+            wire [11:0] brr;
+            assign brr[0] = 1;
+            initial $display("%b", brr);
+            if (YES) begin : blk2
+                assign crr[0] = 1;
+                wire [19:0] crr;
+                initial $display("%b", crr);
+            end
+        end
+    endgenerate
 endmodule