mirror of https://github.com/zachjs/sv2v.git
omit empty subroutine args list
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@ -76,7 +76,7 @@ instance Show Expr where
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show (BinOp o a b) = printf "(%s %s %s)" (show a) (show o) (show b)
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show (Dot e n ) = printf "%s.%s" (show e) n
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show (Mux c a b) = printf "(%s ? %s : %s)" (show c) (show a) (show b)
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show (Call ps f l) = printf "%s%s(%s)" (maybe "" (++ "::") ps) f (show l)
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show (Call ps f l) = printf "%s%s%s" (maybe "" (++ "::") ps) f (show l)
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show (Cast tore e ) = printf "%s'(%s)" (showEither tore) (show e)
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show (DimsFn f v ) = printf "%s(%s)" (show f) (showEither v)
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show (DimFn f v e) = printf "%s(%s, %s)" (show f) (showEither v) (show e)
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@ -93,7 +93,7 @@ data Args
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deriving (Eq, Ord)
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instance Show Args where
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show (Args pnArgs kwArgs) = commas strs
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show (Args pnArgs kwArgs) = "(" ++ (commas strs) ++ ")"
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where
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strs = (map showPnArg pnArgs) ++ (map showKwArg kwArgs)
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showPnArg = maybe "" show
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@ -28,7 +28,7 @@ import Text.Printf (printf)
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import Language.SystemVerilog.AST.ShowHelp (commas, indent, unlines', showPad, showCase)
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import Language.SystemVerilog.AST.Attr (Attr)
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import Language.SystemVerilog.AST.Decl (Decl)
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import Language.SystemVerilog.AST.Expr (Expr, Args)
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import Language.SystemVerilog.AST.Expr (Expr, Args(..))
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import Language.SystemVerilog.AST.LHS (LHS)
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import Language.SystemVerilog.AST.Op (AsgnOp(AsgnOpEq))
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import Language.SystemVerilog.AST.Type (Identifier)
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@ -84,7 +84,8 @@ instance Show Stmt where
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where showInit (l, e) = showAssign (l, AsgnOpEq, e)
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showAssign :: (LHS, AsgnOp, Expr) -> String
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showAssign (l, op, e) = printf "%s %s %s" (show l) (show op) (show e)
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show (Subroutine ps x a) = printf "%s%s(%s);" (maybe "" (++ "::") ps) x (show a)
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show (Subroutine ps x a) = printf "%s%s%s;" (maybe "" (++ "::") ps) x aStr
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where aStr = if a == Args [] [] then "" else show a
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show (AsgnBlk o v e) = printf "%s %s %s;" (show v) (show o) (show e)
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show (Asgn t v e) = printf "%s <= %s%s;" (show v) (maybe "" showPad t) (show e)
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show (While e s) = printf "while (%s) %s" (show e) (show s)
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