additional test coverage for existing logic

test/basic/assign_delay.sv

@@ -0,0 +1,11 @@
+module top;
+    reg x;
+    wire y;
+    assign #5 y = x;
+    initial begin
+        #1 x = 0;
+        #1 x = 1;
+        #20 x = 0;
+        #20 x = 1;
+    end
+endmodule

test/basic/attr.sv

@@ -10,7 +10,7 @@ endmodule
 (* a=1 *) module top;
     (* foo="bar" *) reg x;
     initial begin
-        x = 1;
+        (* bar = "baz" *) x = 1;
         $display(x);
     end
 

test/basic/gate.sv

@@ -12,11 +12,19 @@ module top;
     not (output_not, input_a);
     buf #2 foo_name (output_buf_delay, input_a);
 
+    wire output_nand, output_or, output_nor, output_xor, output_xnor;
+    nand (output_nand, input_a, input_b);
+    or (output_or, input_a, input_b);
+    nor (output_nor, input_a, input_b);
+    xor (output_xor, input_a, input_b);
+    xnor (output_xnor, input_a, input_b);
+
     initial repeat(2) begin
         $monitor("%3d ", $time,
             input_a, input_b,
             output_and, output_and_delay,
-            output_not, output_buf_delay);
+            output_not, output_buf_delay,
+            output_nand, output_or, output_nor, output_xor, output_xnor);
 
         #1;
         #1; input_a = 1;