diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y
index ea7e68e..50893d6 100644
--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -1227,6 +1227,7 @@ GenItemOrNull :: { GenItem }
 
 GenItems :: { [GenItem] }
   : {- empty -}      { [] }
+  | GenItems ";"     { $1 }
   | GenItems GenItem { $1 ++ [$2] }
 
 GenItem :: { GenItem }
diff --git a/test/basic/for_decl.sv b/test/basic/for_decl.sv
index 022ca2c..3c6e8a6 100644
--- a/test/basic/for_decl.sv
+++ b/test/basic/for_decl.sv
@@ -66,6 +66,7 @@ module top;
 
     logic [0:31] c;
     generate
+        ;
         for (genvar n = 0; n < 32; n = n + 1)
             assign c[n] = n & 1;
     endgenerate