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fix concat of based xz literals with uneven chunks

This commit is contained in:
Zachary Snow 2021-02-15 16:58:56 -05:00
parent 8e1f2bbafb
commit 2d7dc00b8d
3 changed files with 25 additions and 2 deletions
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5
src/Language/SystemVerilog/AST/Number.hs
View File

@ -313,8 +313,9 @@ instance Semigroup Number where
if kinds1 == 0 && kinds2 == 0 if kinds1 == 0 && kinds2 == 0
then min base1 base2 then min base1 base2
else Binary else Binary
values = values2 + shiftL values1 size2 trim = flip mod . (2 ^)
kinds = kinds2 + shiftL kinds1 size2 values = trim size2 values2 + shiftL (trim size1 values1) size2
kinds = trim size2 kinds2 + shiftL (trim size1 kinds1) size2
size1 = fromIntegral $ numberBitLength n1 size1 = fromIntegral $ numberBitLength n1
size2 = fromIntegral $ numberBitLength n2 size2 = fromIntegral $ numberBitLength n2
Based _ _ base1 values1 kinds1 = n1 Based _ _ base1 values1 kinds1 = n1

11
test/basic/number_concat.sv
View File

@ -13,5 +13,16 @@ module top;
`TEST('sh3, 'd0); `TEST('sh3, 'd0);
`TEST('sh4, 'd0); `TEST('sh4, 'd0);
`TEST('b0101, 'd0); `TEST('b0101, 'd0);
`TEST(17'hz, 1'b0);
`TEST(17'hzzzzz, 1'b0);
`TEST(17'hzzzzz, 1'bz);
`TEST(17'hzzzzz, 1'h0);
`TEST(17'hzzzzz, 1'h1);
`TEST(17'hzzzzz, 1'hx);
`TEST(17'hzzzzz, 1'hz);
`TEST(2'hx, 1'h0);
`TEST(2'hx, 1'h1);
`TEST(2'hx, 1'hx);
`TEST(2'hx, 1'hz);
end end
endmodule endmodule

11
test/basic/number_concat.v
View File

@ -13,5 +13,16 @@ module top;
`TEST(32'sh3, 32'd0); `TEST(32'sh3, 32'd0);
`TEST(32'sh4, 32'd0); `TEST(32'sh4, 32'd0);
`TEST(32'sb0101, 32'd0); `TEST(32'sb0101, 32'd0);
`TEST(17'hz, 1'b0);
`TEST(17'hzzzzz, 1'b0);
`TEST(17'hzzzzz, 1'bz);
`TEST(17'hzzzzz, 1'h0);
`TEST(17'hzzzzz, 1'h1);
`TEST(17'hzzzzz, 1'hx);
`TEST(17'hzzzzz, 1'hz);
`TEST(2'hx, 1'h0);
`TEST(2'hx, 1'h1);
`TEST(2'hx, 1'hx);
`TEST(2'hx, 1'hz);
end end
endmodule endmodule