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advanced typeof support

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- most binary operators
- ternary expressions
- bitwise negation
- number literals
- size casts
- concat and repeat expressions
This commit is contained in:
Zachary Snow
2020-06-07 13:13:19 -04:00
parent d0a6b0f529
commit 2bc2eb59d8
3 changed files with 162 additions and 2 deletions
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test/basic/typeof.sv
+41
View File
@@ -11,7 +11,9 @@ module top;
initial begin
type(f(0)) x = f(0);
type(x) y = ~x;
$display("%b", x);
$display("%b", y);
$display("%b", $bits(x));
$display("%b", $bits(type(x)));
$display("%b", $bits(logic [0:1+$bits(type(x))]));
@@ -19,4 +21,43 @@ module top;
void'(f(0));
t(1);
end
parameter FLAG = 1;
initial begin
logic [4:1] x = 4'b1011;
type(x ^ 3'b111) y = x ^ 3'b111;
type(x ^ 5'b11111) z = x ^ 5'b11111;
type({8 {x}}) a = {8 {x}};
type({x, y}) b = {x, y};
type(FLAG ? x : y) c = FLAG ? x : y;
type(!FLAG ? x : y) d = !FLAG ? x : y;
$display("%b %d %d", x, $left(x), $right(x));
$display("%b %d %d", y, $left(y), $right(y));
$display("%b %d %d", z, $left(z), $right(z));
$display("%b %d %d", a, $left(a), $right(a));
$display("%b %d %d", b, $left(b), $right(b));
$display("%b %d %d", c, $left(c), $right(c));
$display("%b %d %d", d, $left(d), $right(d));
end
parameter W = 4;
initial begin
logic [W-1:0] x = 4'hA;
type(FLAG ? x : '1) y = FLAG ? x : '1;
type(!FLAG ? y : '1) z = !FLAG ? y : '1;
$display("%b %d %d", x, $left(x), $right(x));
$display("%b %d %d", y, $left(y), $right(y));
$display("%b %d %d", z, $left(z), $right(z));
end
initial begin
type(1) w = 1;
type(-1) x = -1;
type(32'hffff_ffff) y = 32'hffff_ffff;
type(32'shffff_ffff) z = 32'shffff_ffff;
$display("%b %d %d %d", w, w, $left(w), $right(w));
$display("%b %d %d %d", x, x, $left(x), $right(x));
$display("%b %d %d %d", y, y, $left(y), $right(y));
$display("%b %d %d %d", z, z, $left(z), $right(z));
end
endmodule
test/basic/typeof.v
+51 -1
View File
@@ -12,9 +12,11 @@ module top;
endtask
initial begin : block
reg x;
reg x, y;
x = f(0);
y = ~x;
$display("%b", x);
$display("%b", y);
$display("%b", 32'd1);
$display("%b", 32'd1);
$display("%b", 32'd3);
@@ -22,4 +24,52 @@ module top;
x = f(0);
t(1);
end
parameter FLAG = 1;
initial begin : block2
reg [4:1] x;
reg [3:0] y;
reg [4:0] z;
reg [31:0] a;
reg [7:0] b;
reg [3:0] c, d;
x = 4'b1011;
y = x ^ 3'b111;
z = x ^ 5'b11111;
a = {8 {x}};
b = {x, y};
c = FLAG ? x : y;
d = !FLAG ? x : y;
$display("%b %d %d", x, 4, 1);
$display("%b %d %d", y, 3, 0);
$display("%b %d %d", z, 4, 0);
$display("%b %d %d", a, 31, 0);
$display("%b %d %d", b, 7, 0);
$display("%b %d %d", c, 3, 0);
$display("%b %d %d", d, 3, 0);
end
parameter W = 4;
initial begin : block3
reg [W-1:0] x, y, z;
x = 4'hA;
y = FLAG ? x : 4'hF;
z = !FLAG ? y : 4'hF;
$display("%b %d %d", x, W-1, 0);
$display("%b %d %d", y, W-1, 0);
$display("%b %d %d", z, W-1, 0);
end
initial begin : block4
integer w, x, z;
reg [31:0] y;
w = 1;
x = -1;
y = 32'hffff_ffff;
z = 32'shffff_ffff;
$display("%b %d %d %d", w, w, 31, 0);
$display("%b %d %d %d", x, x, 31, 0);
$display("%b %d %d %d", y, y, 31, 0);
$display("%b %d %d %d", z, z, 31, 0);
end
endmodule