mirror of https://github.com/zachjs/sv2v.git
76 lines
1.8 KiB
Verilog
76 lines
1.8 KiB
Verilog
module top;
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function f;
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input x;
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begin
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f = 1'b1 ^ x;
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$display("f(%b) called", x);
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end
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endfunction
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task t;
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input x;
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$display("t(%b) called", x);
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endtask
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initial begin : block
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reg x, y;
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x = f(0);
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y = ~x;
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$display("%b", x);
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$display("%b", y);
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$display("%b", 32'd1);
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$display("%b", 32'd1);
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$display("%b", 32'd3);
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x = f(1);
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x = f(0);
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t(1);
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end
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parameter FLAG = 1;
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initial begin : block2
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reg [4:1] x;
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reg [3:0] y;
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reg [4:0] z;
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reg [31:0] a;
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reg [7:0] b;
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reg [3:0] c, d;
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x = 4'b1011;
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y = x ^ 3'b111;
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z = x ^ 5'b11111;
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a = {8 {x}};
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b = {x, y};
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c = FLAG ? x : y;
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d = !FLAG ? x : y;
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$display("%b %d %d", x, 4, 1);
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$display("%b %d %d", y, 3, 0);
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$display("%b %d %d", z, 4, 0);
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$display("%b %d %d", a, 31, 0);
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$display("%b %d %d", b, 7, 0);
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$display("%b %d %d", c, 3, 0);
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$display("%b %d %d", d, 3, 0);
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end
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parameter W = 4;
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initial begin : block3
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reg [W-1:0] x, y, z;
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x = 4'hA;
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y = FLAG ? x : 4'hF;
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z = !FLAG ? y : 4'hF;
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$display("%b %d %d", x, W-1, 0);
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$display("%b %d %d", y, W-1, 0);
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$display("%b %d %d", z, W-1, 0);
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end
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initial begin : block4
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integer w, x, z;
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reg [31:0] y;
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w = 1;
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x = -1;
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y = 32'hffff_ffff;
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z = 32'shffff_ffff;
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$display("%b %d %d %d", w, w, 31, 0);
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$display("%b %d %d %d", x, x, 31, 0);
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$display("%b %d %d %d", y, y, 31, 0);
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$display("%b %d %d %d", z, z, 31, 0);
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end
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endmodule
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