allow empty parameter_port_list (resolves #83)

2020-03-25 23:55:15 -04:00 · 2020-03-25 23:55:15 -04:00 · 1687b1c5c1
parent e7381c4db2
commit 1687b1c5c1
1 changed files with 1 additions and 0 deletions
--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@ -559,6 +559,7 @@ PackageImportDeclaration :: { [ModuleItem] }

 Params :: { [ModuleItem] }
  : {- empty -}          { [] }
+  | "#" "(" ")"          { [] }
  | "#" "(" ParamsFollow { map (MIPackageItem . Decl) $3 }
 ParamsFollow :: { [Decl] }
  : ParamAsgn ")"              { [$1] }