From 1687b1c5c10d09942aa8c1b3454ad98d5e220ccf Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Wed, 25 Mar 2020 23:55:15 -0400
Subject: [PATCH] allow empty parameter_port_list (resolves #83)

---
 src/Language/SystemVerilog/Parser/Parse.y | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y
index f9134db..c731960 100644
--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -559,6 +559,7 @@ PackageImportDeclaration :: { [ModuleItem] }
 
 Params :: { [ModuleItem] }
   : {- empty -}          { [] }
+  | "#" "(" ")"          { [] }
   | "#" "(" ParamsFollow { map (MIPackageItem . Decl) $3 }
 ParamsFollow :: { [Decl] }
   : ParamAsgn ")"              { [$1] }