mirror of https://github.com/zachjs/sv2v.git
preliminary support for multi-dimensional vector types
This commit is contained in:
Zachary Snow
parent
2ee5b6e039
commit
0c08b9aebb
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@ -35,20 +35,15 @@ convertDescription types (Module name ports items) =
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convertDescription _ other = other
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resolveType :: Types -> Type -> Type
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resolveType _ (Reg mr) = Reg mr
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resolveType _ (Wire mr) = Wire mr
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resolveType _ (Logic mr) = Logic mr
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resolveType types (Alias st mr1) =
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resolveType _ (Reg rs) = Reg rs
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resolveType _ (Wire rs) = Wire rs
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resolveType _ (Logic rs) = Logic rs
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resolveType types (Alias st rs1) =
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case resolveType types $ types Map.! st of
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(Reg mr2) -> Reg $ combineRanges mr1 mr2
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(Wire mr2) -> Wire $ combineRanges mr1 mr2
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(Logic mr2) -> Logic $ combineRanges mr1 mr2
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(Reg rs2) -> Reg $ rs2 ++ rs1
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(Wire rs2) -> Wire $ rs2 ++ rs1
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(Logic rs2) -> Logic $ rs2 ++ rs1
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(Alias _ _) -> error $ "resolveType invariant failed on " ++ st
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where
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combineRanges :: Maybe Range -> Maybe Range -> Maybe Range
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combineRanges Nothing other = other
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combineRanges other Nothing = other
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combineRanges _ _ = error $ "alias " ++ st ++ " leads to 2-D vectorized type"
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convertModuleItem :: Types -> ModuleItem -> ModuleItem
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convertModuleItem types (LocalNet t ident val) =
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@ -71,24 +71,24 @@ instance Show Direction where
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show Inout = "inout"
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data Type
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= Reg (Maybe Range)
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| Wire (Maybe Range)
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| Logic (Maybe Range)
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| Alias String (Maybe Range)
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= Reg [Range]
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| Wire [Range]
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| Logic [Range]
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| Alias String [Range]
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deriving Eq
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instance Show Type where
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show (Reg r) = "reg " ++ (showRange r)
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show (Wire r) = "wire " ++ (showRange r)
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show (Logic r) = "logic " ++ (showRange r)
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show (Alias t r) = t ++ " " ++ (showRange r)
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show (Reg r) = "reg " ++ (showRanges r)
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show (Wire r) = "wire " ++ (showRanges r)
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show (Logic r) = "logic " ++ (showRanges r)
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show (Alias t r) = t ++ " " ++ (showRanges r)
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data ModuleItem
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= Comment String
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| MIParameter Parameter
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| MILocalparam Localparam
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| MIIntegerV IntegerV
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| PortDecl Direction (Maybe Range) Identifier
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| PortDecl Direction [Range] Identifier
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| LocalNet Type Identifier RangesOrAssignment
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| AlwaysC AlwaysKW Stmt
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| Assign LHS Expr
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@ -134,7 +134,7 @@ instance Show ModuleItem where
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MIParameter nest -> show nest
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MILocalparam nest -> show nest
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MIIntegerV nest -> show nest
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PortDecl d r x -> printf "%s %s%s;" (show d) (showRange r) x
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PortDecl d r x -> printf "%s %s%s;" (show d) (showRanges r) x
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LocalNet t x v -> printf "%s%s%s;" (show t) x (showRangesOrAssignment v)
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AlwaysC k b -> printf "%s %s" (show k) (show b)
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Assign a b -> printf "assign %s = %s;" (show a) (show b)
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@ -334,6 +334,8 @@ instance Show Stmt where
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show (Null ) = ";"
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data BlockItemDeclaration
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-- TODO: Maybe BIDReg should use [Range] for the first arg as well, but it's
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-- really not clear to me what useful purpose this would have.
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= BIDReg (Maybe Range) Identifier [Range]
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| BIDParameter Parameter
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| BIDLocalparam Localparam
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@ -177,10 +177,10 @@ Typedef :: { Description }
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: "typedef" Type Identifier ";" { Typedef $2 $3 }
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Type :: { Type }
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: "wire" opt(Range) { Wire $2 }
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| "reg" opt(Range) { Reg $2 }
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| "logic" opt(Range) { Logic $2 }
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| Identifier opt(Range) { Alias $1 $2 }
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: "wire" Dimensions { Wire $2 }
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| "reg" Dimensions { Reg $2 }
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| "logic" Dimensions { Logic $2 }
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| Identifier Dimensions { Alias $1 $2 }
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Module :: { Description }
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: "module" Identifier Params ";" ModuleItems "endmodule" { Module $2 [] ($3 ++ $5) }
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@ -217,12 +217,12 @@ PortDeclsFollow :: { [ModuleItem] }
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| PortDecl(",") PortDeclsFollow { $1 ++ $2 }
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PortDecl(delim) :: { [ModuleItem] }
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: "inout" opt(NetType) opt(Range) Identifiers delim { portDeclToModuleItems Inout $2 $3 (zip $4 (repeat Nothing)) }
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| "input" opt(NetType) opt(Range) Identifiers delim { portDeclToModuleItems Input $2 $3 (zip $4 (repeat Nothing)) }
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| "output" "wire" opt(Range) Identifiers delim { portDeclToModuleItems Output (Just Wire ) $3 (zip $4 (repeat Nothing)) }
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| "output" "reg" opt(Range) VariablePortIdentifiers delim { portDeclToModuleItems Output (Just Reg ) $3 $4 }
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| "output" "logic" opt(Range) VariablePortIdentifiers delim { portDeclToModuleItems Output (Just Logic) $3 $4 }
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NetType :: { Maybe Range -> Type }
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: "inout" opt(NetType) Dimensions Identifiers delim { portDeclToModuleItems Inout $2 $3 (zip $4 (repeat Nothing)) }
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| "input" opt(NetType) Dimensions Identifiers delim { portDeclToModuleItems Input $2 $3 (zip $4 (repeat Nothing)) }
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| "output" "wire" Dimensions Identifiers delim { portDeclToModuleItems Output (Just Wire ) $3 (zip $4 (repeat Nothing)) }
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| "output" "reg" Dimensions VariablePortIdentifiers delim { portDeclToModuleItems Output (Just Reg ) $3 $4 }
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| "output" "logic" Dimensions VariablePortIdentifiers delim { portDeclToModuleItems Output (Just Logic) $3 $4 }
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NetType :: { [Range] -> Type }
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: "wire" { Wire }
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| "logic" { Logic }
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VariablePortIdentifiers :: { [(Identifier, Maybe Expr)] }
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@ -239,10 +239,10 @@ ModuleItems :: { [ModuleItem] }
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ModuleItem :: { [ModuleItem] }
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: PortDecl(";") { $1 }
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-- TODO: Allowing Ranges on aliases creates conflicts
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| Identifier VariableIdentifiers ";" { map (uncurry $ LocalNet (Alias $1 Nothing)) $2 }
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| "wire" opt(Range) VariableIdentifiers ";" { map (uncurry $ LocalNet $ Wire $2) $3 }
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| "reg" opt(Range) VariableIdentifiers ";" { map (uncurry $ LocalNet $ Reg $2) $3 }
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| "logic" opt(Range) VariableIdentifiers ";" { map (uncurry $ LocalNet $ Logic $2) $3 }
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| Identifier VariableIdentifiers ";" { map (uncurry $ LocalNet (Alias $1 [])) $2 }
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| "wire" Dimensions VariableIdentifiers ";" { map (uncurry $ LocalNet $ Wire $2) $3 }
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| "reg" Dimensions VariableIdentifiers ";" { map (uncurry $ LocalNet $ Reg $2) $3 }
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| "logic" Dimensions VariableIdentifiers ";" { map (uncurry $ LocalNet $ Logic $2) $3 }
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| ParameterDeclaration { map MIParameter $1 }
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| LocalparamDeclaration { map MILocalparam $1 }
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| IntegerDeclaration { map MIIntegerV $1 }
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@ -307,13 +307,16 @@ VariableIdentifiers :: { [(Identifier, Either [Range] (Maybe Expr))] }
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: VariableType { [$1] }
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| VariableIdentifiers "," VariableType { $1 ++ [$3] }
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VariableType :: { (Identifier, Either [Range] (Maybe Expr)) }
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: Identifier { ($1, Right $ Nothing) }
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| Identifier "=" Expr { ($1, Right $ Just $3) }
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| Identifier Dimensions { ($1, Left $2) }
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: Identifier { ($1, Right $ Nothing) }
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| Identifier "=" Expr { ($1, Right $ Just $3) }
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| Identifier DimensionsNonEmpty { ($1, Left $2) }
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Dimensions :: { [Range] }
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: Range { [$1] }
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| Dimensions Range { $1 ++ [$2] }
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: {- empty -} { [] }
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| DimensionsNonEmpty { $1 }
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DimensionsNonEmpty :: { [Range] }
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: Range { [$1] }
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| DimensionsNonEmpty Range { $1 ++ [$2] }
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DeclAsgns :: { [(Identifier, Expr)] }
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: DeclAsgn { [$1] }
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@ -387,8 +390,7 @@ BlockVariableIdentifiers :: { [(Identifier, [Range])] }
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: BlockVariableType { [$1] }
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| BlockVariableIdentifiers "," BlockVariableType { $1 ++ [$3] }
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BlockVariableType :: { (Identifier, [Range]) }
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: Identifier { ($1, []) }
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| Identifier Dimensions { ($1, $2) }
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: Identifier Dimensions { ($1, $2) }
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Cases :: { [Case] }
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: {- empty -} { [] }
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@ -501,21 +503,21 @@ toString = tail . init . tokenString
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portDeclToModuleItems
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:: Direction
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-> (Maybe ((Maybe Range) -> Type))
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-> Maybe Range
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-> (Maybe ([Range] -> Type))
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-> [Range]
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-> [(Identifier, Maybe Expr)]
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-> [ModuleItem]
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portDeclToModuleItems dir Nothing mr l =
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map (PortDecl dir mr) $ map toIdentifier $ l
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portDeclToModuleItems dir Nothing rs l =
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map (PortDecl dir rs) $ map toIdentifier $ l
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where
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toIdentifier (x, Just _) = error "ParseError: Incomplete port decl cannot have initialization"
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toIdentifier (x, Nothing) = x
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portDeclToModuleItems dir (Just tf) mr l =
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portDeclToModuleItems dir (Just tf) rs l =
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concat $ map toItems l
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where
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toItems (x, e) =
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[ PortDecl dir mr x
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, LocalNet (tf mr) x (Right e) ]
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[ PortDecl dir rs x
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, LocalNet (tf rs) x (Right e) ]
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getPortNames :: [ModuleItem] -> [Identifier]
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getPortNames items =
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